TLK1201ARCP_16 Datasheet, PDF (3/24 Pages) Texas Instruments – Single Monolithic PLL Design

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TLK1201ARCP, TLK1201AIRCP
ETHERNET TRANSCEIVERS
SLLS580D – FEBRUARY 2004 – REVISED SEPTEMBER 2007
BLOCK DIAGRAM
PRBSEN
LOOPEN
PRBS
Generator
TD(0-9)
10 Bit
Registers
2:1
MUX
Parallel to
Serial
Clock
TXP
TXN
REFCLK
MODESEL
ENABLE
TESTEN
RBC1
RBC0
SYNC/PASS
Control
Logic
PRBS
Verification
Phase Generator
Interpolator
and
Clock Extraction
Clock
2:1
MUX
Clock
RD(0-9)
SYNCEN
RBCMODE
JTMS
JTRSTN
JTDI
TCK
Serial to Parallel
and
Comma Detect
JTAG
Control
Register
2:1
MUX
JTDO
Data
RXP
RXN
LOS
TERMINAL
NAME
NO.
SIGNAL
MODESEL
15
LOS
26
RBCMODE
32
RBC0
31
RBC1
30
Terminal Functions
I/O
DESCRIPTION
I
P/D ⁽¹⁾
O
I
P/D ⁽¹⁾
O
Mode select. This terminal selects between the 10-bit interface and a reduced 5-bit DDR
interface. When low, the 10-bit interface (TBI) is selected. When pulled high, the 5-bit DDR mode
is selected. The default mode is the TBI.
Loss of signal. Indicates a loss of signal on the high-speed differential inputs RXP and RXN.
If the magnitude of RXP-RXN > 150 mV, then LOS = 1 which is a valid input signal.
If the magnitude of RXP-RXN > 50 mV and < 150 mV, then LOS is undefined.
If the magnitude of RXP-RXN < 50 mV, then LOS = 0 which is a loss of signal.
Receive clock mode select. When RBCMODE and MODESEL are low, half-rate clocks are output
on RBC0 and RBC1. When MODESEL is low and RBCMODE is high, a full baud-rate clock is
output on RBC0 and RBC1 is held low. When MODESEL is high, RBCMODE is ignored and a full
baud-rate clock is output on RBC0 and RBC1 is held low.
Receive byte clock. RBC0 and RBC1 are recovered clocks used for synchronizing the 10-bit
output data on RD0–RD9. The operation of these clocks is dependent upon the receive clock
mode selected.
In the half-rate mode, the 10-bit output data words are valid on the rising edges of RBC0 and
RBC1. These clocks are adjusted to half-word boundaries in conjunction with synchronous
detect. The clocks are always expanded during data realignment and never slivered or truncated.
RBC0 registers bytes 1 and 3 of received data. RBC1 registers bytes 0 and 2 of received data.
In the normal rate mode, only RBC0 is valid and operates at 1/10th the serial data rate. Data is
aligned to the rising edge.
In the DDR mode, only RBC0 is valid and operates at 1/10th the serial data rate. Data is aligned
on both the rising and falling edges.
(1) P/D = Internal pulldown
Copyright © 2004–2007, Texas Instruments Incorporated
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