TLK1201ARCP_16 Datasheet, PDF (4/24 Pages) Texas Instruments – Single Monolithic PLL Design

TLK1201ARCP, TLK1201AIRCP
ETHERNET TRANSCEIVERS
SLLS580D – FEBRUARY 2004 – REVISED SEPTEMBER 2007
www.ti.com
TERMINAL
I/O
NAME
NO.
RD0–RD9
45, 44,
O
43, 41,
40, 39,
38, 36,
35, 34
REFCLK
22
I
RXP
RXN
SYNCEN
SYNC/PASS
54
PECL I
52
24
I
P/U ⁽²⁾
47
O
TD0–TD9
2-4, 6-9,
I
11-13
TXP
TXN
TEST
ENABLE
JTDI
JTDO
JTMS
JTRSTN
LOOPEN
62
PECL
61
O
28
I
P/U ⁽³⁾
48
I
P/U ⁽³⁾
27
O
55
I
P/U ⁽³⁾
56
I
P/U ⁽³⁾
19
I
P/D ⁽⁴⁾
PRBSEN
16
I
P/D ⁽⁴⁾
TCK
49
TESTEN
17
(2) P/U = Internal pullup
(3) P/U = Internal pullup
(4) P/D = Internal pulldown
I
I
P/D ⁽⁴⁾
Terminal Functions (continued)
DESCRIPTION
Receive data. When in TBI mode (MODESEL = low), these outputs carry 10-bit parallel data
output from the transceiver to the protocol layer. The data is referenced to terminals RBC0 and
RBC1, depending on the receive clock mode selected. RD0 is the first bit received. When in the
DDR mode (MODESEL = high), only RD0–RD4 are valid. RD5–RD9 are held low. The 5-bit
parallel data is clocked out of the transceiver on the rising edge of RBC0.
Reference clock. REFCLK is an external input clock that synchronizes the receiver and
transmitter interface (60 MHz to 130 MHz). The transmitter uses this clock to register the input
data (TD0–TD9) for serialization. In the TBI mode that data is registered on the rising edge of
REFCLK.
In the DDR mode, the data is registered on both the rising and falling edges of REFCLK with the
most significant bits aligned on the rising edge of REFCLK.
Differential input receive. RXP and RXN together are the differential serial input interface from a
copper or an optical I/F module.
Synchronous function enable. When SYNCEN is high, the internal synchronization function is
activated. When this function is activated, the transceiver detects the K28.5 comma character
(0011111 negative beginning disparity) in the serial data stream and realigns data on byte
boundaries if required. When SYNCEN is low, serial input data is unframed in RD0–RD9.
Synchronous detect. The SYNC output is asserted high upon detection of the comma pattern in
the serial data path. SYNC pulses are output only when SYNCEN is activated (asserted high). In
PRBS test mode (PRBSEN = high), SYNC/PASS outputs the status of the PRBS test results
(high = pass).
Transmit data. When in the TBI mode (MODESEL = low) these inputs carry 10-bit parallel data
output from a protocol device to the transceiver for serialization and transmission. This 10-bit
parallel data is clocked into the transceiver on the rising edge of REFCLK and transmitted as a
serial stream with TD0 sent as the first bit.
When in the DDR mode (MODESEL = high) only TD0–TD4 are valid. The 5-bit parallel data is
clocked into the transceiver on the rising and falling edge of REFCLK and transmitted as a serial
stream with TD0 sent as the first bit.
Differential output transmit. TXP and TXN are differential serial outputs that interface to a copper
or an optical I/F module. TXP and TXN are put in a high-impedance state when LOOPEN is high
and are active when LOOPEN is low.
When this terminal is low, the device is disabled for Iddq testing. RD0–RD9, RBCn, TXP, and
TXN are high impedance. The pullup and pulldown resistors on any input are disabled. When
ENABLE is high, the device operates normally.
Test data input. IEEE1149.1 (JTAG)
Test data output. IEEE1149.1 (JTAG)
Test mode select. IEEE1149.1 (JTAG)
Reset signal. IEEE1149.1 (JTAG)
Loop enable. When LOOPEN is high (active), the internal loop-back path is activated. The
transmitted serial data is directly routed to the inputs of the receiver. This provides a self-test
capability in conjunction with the protocol device. The TXP and TXN outputs are held in a
high-impedance state during the loop-back test. LOOPEN is held low during standard operational
state with external serial outputs and inputs active.
PRBS enable. When PRBSEN is high, the PRBS generation circuitry is enabled. The PRBS
verification circuit in the receive side is also enabled. A PRBS signal can be fed to the receive
inputs and checked for errors, that are reported by the SYNC/PASS terminal indicating low.
Test clock. IEEE1149.1 (JTAG)
Manufacturing test terminal
4
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