TLK1201ARCP_16 Datasheet, PDF (5/24 Pages) Texas Instruments – Single Monolithic PLL Design

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TERMINAL
NAME
NO.
POWER
VDD
5, 10,
20, 23,
29, 37,
42, 50,
63
VDDA
53, 57,
59, 60
VDDPLL
18
GROUND
GND
1, 14,
21,25,
33, 46
GNDA
51, 58
GNDPLL
64
TLK1201ARCP, TLK1201AIRCP
ETHERNET TRANSCEIVERS
SLLS580D – FEBRUARY 2004 – REVISED SEPTEMBER 2007
Terminal Functions (continued)
I/O
DESCRIPTION
Supply Digital logic power. Provides power for all digital circuitry and digital I/O buffers.
Supply Analog power. VDDA provides power for the high-speed analog circuits, receiver, and transmitter
Supply PLL power. Provides power for the PLL circuitry. This terminal requires additional filtering.
Ground Digital logic ground. Provides a ground for the logic circuits and digital I/O buffers.
Ground Analog ground. GNDA provides a ground for the high-speed analog circuits RX and TX.
Ground PLL ground. Provides a ground for the PLL circuitry.
DETAILED DESCRIPTION
Data Transmission
This device supports both the defined 10-bit interface (TBI) and a reduced 5-bit interface utilizing DDR clocking.
When MODESEL is low, the TBI mode is selected. When MODESEL is high, the DDR mode is selected.
In the TBI mode, the transmitter portion registers incoming 10-bit wide data words (8b/10b encoded data,
TD0–TD9) on the rising edge of REFCLK. The REFCLK is also used by the serializer, which multiplies the clock
by a factor of 10, providing a signal that is fed to the shift register. The 8b/10b encoded data is transmitted
sequentially bits 0 through 9 over the differential high-speed I/O channel.
In the DDR mode, the transmitter accepts 5-bit wide 8b/10b encoded data on pins TD0–TD4. In this mode, data
is aligned to both the rising and falling edges of REFCLK. The data is then formed into a 10-bit wide word and
sent to the serializer. The rising edge REFCLK clocks in bits 0–4, and the falling edge of REFCLK clocks in bits
5–9. Bit 0 is the first bit transmitted.
Transmission Latency
Data transmission latency is defined as the delay from the initial 10-bit word load to the serial transmission of bit
9. The minimum latency in TBI mode is 19 bit times. The maximum latency in TBI mode is 20 bit times. The
minimum latency in DDR mode is 29 bit times, and maximum latency in DDR mode is 30 bit times.
Measured 10-Bits
Next 10-Bit Code
TXP, TXN
t_{d(Tx latency)}
b7 b8 b9 b0 b1 b2 b3
TD(0−9)
10-Bit Code
REFCLK
Figure 1. Transmitter Latency Full Rate Mode
Copyright © 2004–2007, Texas Instruments Incorporated
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