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TLC5973 Datasheet, PDF (9/34 Pages) Texas Instruments – TLC5973 3-Channel, 12-Bit, PWM Constant-Current LED Driver with Single-Wire Interface (EasySet)
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Timing Diagrams (continued)
TLC5973
SBVS225B – MARCH 2013 – REVISED MAY 2014
VCC
SDI
Data Transfer
Period Memory
(Internal in 1st Device)
Recognized Data,
SIN Signal
(Internal in 1st Device)
SCLK Signal
(Internal in 1st Device)
48-Bit Shift Register LSB
(Internal in 1st Device)
48-Bit Shift Register LSB+1
(Internal in 1st Device)
48-Bit Shift Register MSB-1
(Internal in 1st Device)
48-Bit Shift Register MSB
(Internal in 1st Device)
OUTEN Signal
(Internal)
GSLAT Signal
(Internal in 1st Device)
36-Bit GS Data Latch
(Internal in 1st Device)
SDO
SCLK Signal
(Internal in 2nd Device)
48-Bit Shift Register LSB
(Internal in 2nd Device)
GSLAT Signal
(Internal in 2nd Device)
GS Data Latch
(Internal in 2nd Device)
1st Device 2nd
1st Data (0) Data (0)
3rd
Data (1)
4th
Data (1)
5th
Data (1)
48th
Data (0)
2nd Device 2nd
48th
1st Data (0) Data (0) Data (0)
1st Device
1st Data (0)
fCLK(SDI)
fCLK(SDI) tSDI
tWH
tWL
Data transfer period (tCYCLE) is stored.
tH0 (for EOS)
1st Data (0) 2nd Data (0) 3rd Data (1) 4th Data (1)
5th Data (1)
47th
Data
48th Data (0)
48th Data (0)
tH1 (for GSLAT)
Data transfer period (tCYCLE) is stored.
1st Data (0)
1st Data (0)
2nd Data (0)
1st Data (0)
3rd Data (1)
2nd Data (0)
4th Data (1)
47th
Data
5th Data (1)
3rd Data (1)
46th
Data
4th Data (1)
1st Data (0)
Low = SDI data are not output from SDO.
48th Data (0)
47th Data
2nd Data (0)
1st Data (0)
High = SDI data are output from SDO.
1st Data (0)
48th Data (0)
3rd Data (0)
2nd Data (0)
(All GS data are ‘0’ when VCC powers up.)
tD0
tWO
tF0
tR0
New GS Data
47th Data (0)
48th Data (0)
(All GS data are ‘0’ when VCC powers up.)
New GS Data
OFF
OUT0
ON
OFF
OUT1
ON
OFF
OUT2
ON
(VOUTnH)
(VOUTnL)
(1) OUTn on-time changes, depending on the data in the 36-bit GS data latch.
Figure 11. Data Write and OUTn Switching Timing
tF1
(1)
tR1
(1)
tD1
(1)
tD1
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