TLC5973 Datasheet, PDF (21/34 Pages) Texas Instruments – TLC5973 3-Channel, 12-Bit, PWM Constant-Current LED Driver with Single-Wire Interface (EasySet)

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TLC5973
SBVS225B – MARCH 2013 – REVISED MAY 2014
8.6 Register Maps
8.6.1 Register and Data Latch Configuration
The TLC5973 has a 48-bit shift register and a 36-bit data latch that stores GS data. When the internal GS data
latch pulse is generated and the data of the 12 MSBs in the shift register are 3AAh, the lower 36-bit data in the
48-bit shift register are copied into the 36-bit GS data latch. If the data of the 12 MSBs is not 3AAh, the 36-bit
data are not copied into the 36-bit GS data latch. Figure 21 shows the shift register and GS data latch
configurations. Table 3 shows the 48-bit shift register bit assignment.
48-Bit Shift Register
MSB
Write
Command
Bit 11
47
---
Write
OUT0
Command GS Data
Bit 0
Bit 11
36
35
---
LSB
OUT0
GS Data
Bit 0
OUT1
GS Data
Bit 11
OUT1
GS Data
Bit 0
OUT2
GS Data
Bit 11
OUT2
GS Data
Bit 0
24
23
---
12
11
---
0
Shift Data (Internal)
Shift Clock (Internal)
12 Bits
12-Bit Write
Command
Decoder
36-Bit GS Data Latch
MSB
35
---
OUT0
GS Data
Bit 11
24
OUT0
GS Data
Bit 0
23
OUT1
GS Data
Bit 11
36 Bits
The internal latch pulse is generated after 8 t_CYCLES without SDI clocking.
---
12
11
---
OUT1
GS Data
Bit 0
OUT2
GS Data
Bit 11
LSB
0
OUT2
GS Data
Bit 0
GS Data
Latch Pulse
(Internal)
Write Command = 3AAh (001110101010b)
36 Bits
To Grayscale Timing
Control Circuit
Figure 21. Common Shift Register and Control Data Latches Configuration
BITS
0 to 11
12 to 23
24 to 35
36 to 47
Table 3. 48-Bit Shift Register Data Bit Assignment
BIT NAME
GSOUT2
GSOUT1
GSOUT0
WRTCMD
CONTROLLED CHANNEL/FUNCTIONS
GS data bits 0 to 11 for OUT2
GS data bits 0 to 11 for OUT1
GS data bits 0 to 11 for OUT0
Data write command (3AAh) for GS data.
The lower 36-bit GS data in the 48-bit shift register are copied to the GS data latch
when the internal GS latch is generated (when these data bits are 3AAh,
001110101010b).
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