TLC5973 Datasheet, PDF (18/34 Pages) Texas Instruments – TLC5973 3-Channel, 12-Bit, PWM Constant-Current LED Driver with Single-Wire Interface (EasySet)

TLC5973
SBVS225B – MARCH 2013 – REVISED MAY 2014
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8.4.2.4 GS Data Latch (GSLAT) Sequence
A GS data latch (GSLAT) sequence must be input after the 48-bit data for all cascaded devices are written.
When SDI is held low for the data latch hold time (t_H1), the 48-bit shift register data in all devices are copied to
the GS data latch in each device. Furthermore, PWM control starts with the new GS data at the same time.
Figure 17 shows the GSLAT timing.
The first SDI rising edge of the last input data.
SDI
48-Bit Shift
Register
(Internal)
GSLAT Signal
(Internal)
8 x t_CYCLE (min)
Shift register data are
written after GSLAT is input.
GS Data in
36-Bit
Data Latch
(Internal)
OUTEN Signal
(Internal)
High = pulse signal output from SDO.
New GS Data
Low = pulse signal not output from SDO.
SDO
Figure 17. GS Data Latch Sequence (GSLAT)
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