TLC34058 Datasheet, PDF (9/26 Pages) Texas Instruments – 256 × 24 COLOR PALETTE

TLC34058
256 × 24 COLOR PALETTE
SLAS050 – D3961, NOVEMBER 1991
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, R_set = 523 Ω, V_ref = 1.235 V (see Note 2)
PARAMETER
TIMING†
REFERENCE
LIMIT
135 MHz
VERSION
125 MHz 110 MHz
UNITS
80 MHz
CE low to data bus enabled
5
MIN
10
10
10
10
ns
CE low to data valid
6
MAX
75
75
75
100
ns
CE high to data bus disabled
7
MAX
15
15
15
15
ns
Analog output delay time (see Note 3)
18
TYP
20
20
20
20
ns
Analog output rise or fall time (see Note 4)
19
TYP
2
2
2
3
ns
Analog output setting time (see Note 5)
20
MAX
8
8
9
12
ns
Glitch impulse (see Note 6)
TYP
50
50
50
50
pV-s
Analog output skew
TYP
0
0
0
0
ns
MAX
2
2
2
2
ns
Pipeline delay
MIN
6
6
6
6
clock
MAX
10
10
10
10
cycles
† _{See Figures 1 and 2.}
NOTES: 2. TTL input signals are 0 to 3 V with less than 3 ns rise/fall times between 10% and 90% levels. ECL input signals are VDD – 1.8 to
VDD – 0.8 V with less than 2 ns rise/fall times between 20% and 80% levels. For input and output signals, timing reference points
are at the 50% signal level. Analog output loads are less than 10 pF. D0 – D7 output loads are less than 40 pF.
3. Measured from 50% point of rising clock edge to 50% point of full-scale transition.
4. Measured between 10% and 90% of full-scale transition.
5. Measured from 50% point of full-scale transition to output settling within ± 1 LSB. Settling time does not include clock and data
feedthrough.
6. Glitch impulse includes clock and data feedthrough. The – 3-dB test bandwidth is twice the clock rate.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
9