TLC34058 Datasheet, PDF (15/26 Pages) Texas Instruments – 256 × 24 COLOR PALETTE

PRINCIPLES OF OPERATION
TLC34058
256 × 24 COLOR PALETTE
SLAS050 – D3961, NOVEMBER 1991
control register write/read
The four control registers are addressed with internal address register values 04 – 07. Upon writing to or reading
from the internal address register, the additional address bits ADDRab are automatically reset to 0. To facilitate
read-modify-write operations, the internal address register does not increment after writing to or reading from
the control registers. All control registers may be accessed at any time. When accessing the control registers,
C0 and C1 are respective set low and high. Refer to Table 3 for quick reference.
R/W
C1
L
L
L
H
H
L
H
H
X = irrelevant
Table 3. Writing to or Reading from Control Registers
C0 ADDRba ADDRab
FUNCTION
L
X
X
write ADDR0 – 7: D0 – D7 → ADDR0 – 7; 0 → ADDRa,b
L
L
L
write control register: D0 – D7 → control register
L
X
X
read ADDR0 – 7: ADDR0 – 7 → D0 – D7; 0 → ADDRa,b
L
L
L
read control register: control register → D0 – D7
summary of internal address register operations
Table 4 provides a summary of operations that use the internal address register. Figure 1 presents the read/write
timing for the device.
If an invalid address is loaded into the internal address register, the device will ignore subsequent data from the
MPU during a write operation and will send incorrect data to the MPU during a read operation.
Table 4. Internal Address Register Operations
INTERNAL ADDRESS
REGISTER VALUE
C1
(ADDR0 – 7) (HEX)
00 – FF
L
00 – 03
H
04
H
05
H
06
H
07
H
ADDRab
C0
MPU ACCESS
(counts
modulo 3)
00
H
color palette RAM
01
11
00
H
over color 0 to 3
01
110
L
read mask register
L
blink mask register
L
command register
L
test register
COLOR
red value
green value
blue value
red value
green value
blue value
interruption of display refresh pixel data (via simultaneous pixel data retrieval and MPU write)
If the MPU is writing to a particular palette RAM location or overlay register (during the blue cycle) and the display
refresh process is accessing pixel data from the same RAM location or overlay register, one or more pixels on
the display screen may be disturbed. If the MPU write data is valid during the complete chip enable period, a
maximum of one pixel will be disturbed.
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