TLC34058 Datasheet, PDF (21/26 Pages) Texas Instruments – 256 × 24 COLOR PALETTE

APPLICATION INFORMATION
TLC34058
256 × 24 COLOR PALETTE
SLAS050 – D3961, NOVEMBER 1991
clock interfacing
To facilitate the generation of high-frequency clock signals, the CLK and CLK pins are designed to accept
differential signals that can be generated with 5-V (single supply) ECL logic. Due to noise margins of the CMOS
process, the CLK and CLK inputs must be differential signals. Connecting a single-ended clock signal to CLK
and connecting CLK to GND will not work.
The CLK and CLK pins require termination resistors (220-Ω to V_DD and 330-Ω to GND) that should be as close
to the device as possible.
LD is typically generated by dividing the clock frequency by four (4:1 multiplexing) or five (5:1 multiplexing) and
translating the resulting signal to TTL levels. Since no phase relationship between the LD and CLK signals is
required, any propagation delay in LD caused by the divider circuitry will not affect device performance.
The pixel, overlay, sync and blank data are latched on the rising edge of LD. LD may also be used as the shift
clock for the video DRAMs. In short, LD provides the fundamental timing for the video system.
The Bt438 Clock Generator (from Brooktree) is recommended for generating the CLK, CLK, LD, and REF
signals. It supports both 4:1 and 5:1 multiplexing. Alternatively, the Bt438 can interface the device to a TTL clock.
Figure 5 illustrates the interconnection between the Bt438 and the device.
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