TLC34058 Datasheet, PDF (16/26 Pages) Texas Instruments – 256 × 24 COLOR PALETTE

TLC34058
256 × 24 COLOR PALETTE
SLAS050 – D3961, NOVEMBER 1991
PRINCIPLES OF OPERATION
frame buffer interface and timing
An internal latch and multiplexer enables the frame buffer to send the pixel data to the device at TTL rates. On
the rising edges of LD, information for four or five consecutive pixels is latched into the device. This information
includes the palette RAM address (up to 8 bits), the overlay register address (up to 2 bits), and the sync and
blank information for each of the four or five consecutive pixels. The timing diagram for this pixel data input
transfer is shown in Figure 2, along with the video output waveforms (IOR, IOG, and IOB). Note that with this
architecture, the sync and blank timing can only be recognized with four- or five-pixel resolution.
The display refresh process follows the first-in first-out format. Color data is output from the device in the same
order in which palette RAM and overlay addresses are input. This process continues until all four or five pixels
have been output, at which point the cycle will repeat.
The overlay timing can be controlled by the pixel timing. However, this approach requires that the frame buffer
emit additional bit planes to control the overlay selection on a pixel basis. Alternatively, the overlay timing can
be controlled by external character or cursor generation timing (see the color selection section).
No phase relationship between the LD and CLK signals is required (see Figure 2). Therefore, the LD signal can
be derived by externally dividing the CLK signal by four or five. Any propagation delay in LD caused by the divider
circuitry will not render the device nonfunctional. Regardless of the phase relationship between LD and CLK,
the pixel, overlay, sync, and blank data are latched on the rising edge of LD.
The device has an internal load signal (not brought out to a pin), which is synchronous to CLK and will follow
LD by at least one and not more than four clock cycles. This internal load signal transfers the LD-latched data
into a second set of latches, which are then internally multiplexed at the pixel clock or CLK signal frequency.
For 4:1 or 5:1 multiplexing, a rising edge of LD should occur every four or five clock cycles. Otherwise, the
internal load signal generation circuitry cannot lock onto or synchronize with LD.
color selection
The read mask, blink mask, and command registers process eight bits of color information (P0 – P7) and two
bits of overlay information (OL0 – OL1) for each pixel every clock cycle. Control registers allow individual bit
planes to be enabled/disabled for display and/or blinked at one of four blink rates and duty cycles (see the
command register section, bits CR4 – CR5).
By monitoring the BLK input to determine vertical retrace intervals, the device ensures that a color change due
to blinking occurs only during the nonactive display time. Thus, a color change does not occur in the middle of
the screen. A vertical retrace is sensed when BLK is low for at least 256 LD cycles. The color information is then
selected from the palette RAM or overlay registers, in accordance with the processed input pixel data.
Table 5 presents the effect of the processed input pixel data upon color selection. Note that P0 is the least
significant bit (LSB) of the color palette RAM. When CR6 is high and both OL1 and OL0 are low, color information
resides in the color palette RAM. When CR6 is low or either of the overlay inputs is high, the overlay registers
provide the DAC inputs.
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