TLC34058 Datasheet, PDF (14/26 Pages) Texas Instruments – 256 × 24 COLOR PALETTE

TLC34058
256 × 24 COLOR PALETTE
SLAS050 – D3961, NOVEMBER 1991
PRINCIPLES OF OPERATION
R/W
C1
L
L
L
L
L
L
L
L
H
L
H
L
H
L
H
L
X = irrelevant
Table 1. Writing to or Reading from Palette RAM
C0 ADDRb ADDRa
FUNCTION
L
X
X
write ADDR0–7: D0 – D7 → ADDR0 – 7; 0 → ADDRa,b
H
L
L
write red color: D0 – D7 → RREG; increment ADDRa,b
H
L
H
write green color: D0 – D7 → GREG; increment ADDRa,b
H
H
L
write blue color: D0 – D7 → BREG; increment ADDRa,b; increment ADDR0 – 7; write
palette RAM
L
X
X
read ADDR0 – 7: ADDR0 – 7 → D0 – D7; 0 → ADDRa,b
H
L
L
read red color: R0 – R7 → D0 – D7; increment ADDRa,b
H
L
H
read green color: G0 – G7 → D0 – D7; increment ADDRa,b
H
H
L
read blue color: B0 – B7 → D0 – D7; increment ADDRa,b; increment ADDR0 – 7
overlay register write/read
With a few exceptions, the overlay register operation is identical to the palette RAM write/read operation (refer
to the palette RAM write/read section). Upon writing to or reading from the internal address register, the
additional address register ADDRab is automatically reset to 0. ADDRab counts modulo 3 as the red, green,
and blue information is written to or read from a particular overlay register. The four overlay registers are
addressed with internal address register values 00 – 03. After writing/reading blue information, the internal
address register bits ADDR0 – 7 are incremented to the next overlay location. After accessing overlay register
value 03, the internal address register does not reset to 00 but is advanced to 04.
For writing to or reading from the internal address register, C0 and C1 are set low. When accessing the overlay
registers, C0 and C1 are set high. Refer to Table 2 for quick reference.
R/W
C1
L
L
L
H
L
H
L
H
H
L
H
H
H
H
H
H
X = irrelevant
Table 2. Writing to or Reading from Overlay Registers
C0 ADDRb ADDRa
FUNCTION
L
X
X
write ADDR0 - 7: D0 – D7 → ADDR0–7; 0 → ADDRa,b
H
L
L
write red color: D0 – D7 → RREG; increment ADDRa,b
H
L
H
write green color: D0 – D7 → GREG; increment ADDRa,b
H
H
L
write blue color: D0 – D7 → BREG; increment ADDRa,b; increment ADDR0 – 7; write
overlay register
L
X
X
read ADDR0 – 7: ADDR0 – 7 → D0 – D7; 0 → ADDRa,b
H
L
L
read red color: R0 – R7 → D0 – D7; increment ADDRa,b
H
L
H
read green color: G0 – G7 → D0 – D7; increment ADDRa,b
H
H
L
read blue color: B0 – B7 → D0 – D7; increment ADDRa,b; increment ADDR0 – 7
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