TLC34058 Datasheet, PDF (13/26 Pages) Texas Instruments – 256 × 24 COLOR PALETTE

PRINCIPLES OF OPERATION
TLC34058
256 × 24 COLOR PALETTE
SLAS050 – D3961, NOVEMBER 1991
microprocessor unit (MPU) interface
As shown in the functional block diagram, the MPU has direct access to the internal control registers and color
overlay palettes via a standard MPU interface. Since the palette RAM and overlay registers have dual ports,
they can be updated without affecting the display refresh process. One port is allocated for updating or reading
data and the other for display.
palette RAM write or read
The palette RAM location is addressed by the internal 8-bit address register (ADDR0 – 7). The MPU can either
write to or read from this register. The register eliminates the need for external address multiplexers.
ADDR0 – ADDR7 are updated via D0 – D7. To address the red, green, and blue part of a particular RAM location,
the internal address register is provided with two additional bits, ADDRa and ADDRb. These address bits count
modulo 3 and are reset to 0 when the MPU accesses the internal address register.
After writing to or reading from the internal address register, the MPU executes three write or read cycles (red,
green and blue). The register ADDRab is incremented after each of these cycles so that the red, green, and blue
information is addressed from the correct part of the particular RAM location. During the blue write cycle, the
red, green, and blue color information is adjoined to form a 24-bit word, which is then written to the particular
RAM location. After the blue write/read cycle, the internal address register bits ADDR0 – 7 are incremented to
access the next RAM location. For an entire palette RAM write or read, the bits ADDR0 – 7 are reset to 00 after
accessing the FF (256) palette RAM location.
Two additional control bits, C0 and C1, are used to differentiate the palette RAM read/write function from other
operations that utilize the internal address register. C0 and C1 are respectively set high and low for writing to
or reading from the palette RAM. Table 1 summarizes this differentiation, along with other internal address
register operations. Note that C0 and C1 are each set low for writing to or reading from the internal address
register.
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