TCM8002_08 Datasheet, PDF (9/25 Pages) Texas Instruments – DATA PROCESSOR FOR CELLULAR TELEPHONE

TCM8002
DATA PROCESSOR FOR CELLULAR TELEPHONE
SLWS008C − SEPTEMBER 1994 − REVISED JUNE 1996
PRINCIPLES OF OPERATION
receive path
The following paragraphs detail the TCM8002 receive path, which includes the function blocks as given in the
functional block diagram.
Data Recovery
The input to the Data Recovery block is RXIN and the signal applied to this terminal should be a digital version
of the output from the FM demodulator/discriminator in the phone. Data recovery is performed by a digital
phase-lock circuit with its center frequency at the designated bit rate (i.e., 10 kbps for AMPS and 8 kbps for
TACS).
The dotting preamble produces a square wave with a frequency one-half of the bit rate and transitions at the
center of each bit period. This is used by the data recovery circuit to acquire bit synchronization with the
acquisition coefficient (DATAREC coef 1). After synchronization is achieved, the lock coefficient is used
(DATAREC coef 2) to allow phase adjustment during subsequent occurrences of dotting.
RX Control
The receiver control circuit detects the dotting sequence and the frame synchronization code (11100010010).
Once frame synchonization has been achieved, the received data stream is separated. The FOCC stream is
separated into busy/idle bits, bits of word A, and bits of word B. Recovered FVC bits are separated into bits of
the received word, dotting bits, and word sync bits. For both FOCC and FVC, a word repeat count is also
maintained. For the FOCC, a count is maintained of the number of consecutive sync words matched and the
number not matched. Two matches are required to acquire and confirm frame synchronization. Five
consecutive mismatches indicate loss-of-frame synchronization.
During FOCC reception, the busy/idle bits are fed directly to the Arbitration Logic block. A majority vote of the
most recent three busy/idle bits is made available at RCCBUSY and at status word 1, bit 4.
During FVC message reception, the receive audio enable output (RAEN) changes state. The output changes
on frame synchronization and returns to the initial state 928 bit periods later. Status word 2, bit 1 is set for this
period.
The receive audio circuit in a connected TCM8010 can be automatically controlled through the TCM8010
interface (see control word 2). During FVC wideband data reception, a copy of the previous TCM8010 control
word 1 is resent with bits 0 and 1 set to 0, muting the received audio path. After the end of data reception, the
original TCM8010 control word 1 is resent.
Majority Voting
The Majority Voting function performs a bit-wise majority vote on the repeated FOCC or FVC words. All five
repeats of the (A or B) FOCC word are used and up to 11 repeats of the FVC word are used. The result is to
recognize each of the 40 bits as a logic 0 or logic 1.
BCH Decoder
The error-correction circuit corrects the received BCH code. This is a 40-bit code word consisting of 28 data
bits and 12 parity bits. The circuit is able to correct errors in the received majority-voted 40-bit word from the
12 parity bits. Up to two errors in either the data or parity can be detected. The corrected 28 data bits together
with 4 correction status bits may be read from the RX data word 0 to RX data word 3 locations. In low-power
mode, this block is turned on only when there is data to be corrected and is selected by control word 4, bit 0.
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