TCM8002_08 Datasheet, PDF (12/25 Pages) Texas Instruments – DATA PROCESSOR FOR CELLULAR TELEPHONE

TCM8002
DATA PROCESSOR FOR CELLULAR TELEPHONE
SLWS008C − SEPTEMBER 1994 − REVISED JUNE 1996
PRINCIPLES OF OPERATION
Programmable I/O Extension
The Programmable I/O Extension provides processor port expansion. PIO1(0−7), PIO2(0−7), and PIO3(0−3)
can be configured as either inputs or outputs. For those pins configured as outputs, the output values are set
through the microprocessor interface. The values at all of the ports can be read through the microprocessor
interface.
Eight output terminals can also be configured as programmable outputs instead of the named functions. The
programmable outputs are the terminals with the /PO4(. . .) in their names. All inputs feature Schmitt triggers
and all the PIO terminals feature optional 10-µA pullups.
RESET
A low logic level at RESET performs a chip reset. The default values listed in the write address map are loaded.
microcontroller interface
The TCM8002 microcontroller interface is described in subsequent paragraphs.
write
For a write operation, CS is taken low and data on DATAIN is clocked into the TCM8002 on each rising edge
of DCLK. It is important that CS is taken low when DCLK is low for the correct operation of the read/write
selection logic in the microprocessor interface. The input sequence is start bit (logic 1), 7-bit address, then 8 bits
of data. The operation is completed by CS returning to a high logic level with DCLK low. If DCLK is not low, an
extra clock pulse is required. The address and data to be written to control the TCM8002 and to transmit
Manchester-encoded signals are detailed in the write address map (Table 2). Eight bits of data are always
written to the interface and data is right-justified. When writing to addresses 20 − 26, it is necessary to supply
clock cycles to write dummy data to the microprocessor interface to start the actions. The state of DATAIN during
these write-data clock cycles is not important.
read
For a read operation, the start bit is cleared to 0. Following the seven address bits, DATAOUT is enabled and
the output data is updated on each falling edge of DCLK. DCLK must be low when CS is taken low for correct
operation of the read/write selection logic in the microprocessor interface. The operation is completed by CS
returning to a high logic level with DCLK low. When DCLK is not low, an extra clock pulse is required.
When reading from the event register only, DCLK must be changed from its nominal period of 1 µs to a period
of 2 µs so that the start bit is 2 µs long. This can be accomplished by skipping a clock pulse while the start bit
is low. Reading from all other registers requires no adjustment to the DCLK nominal period of 1 µs.
DATAOUT returns to the high-impedance state when CS returns high. During the read operation, eight bits of
data are output on DATAOUT in the order of bit 7 to bit 0. During a read from the event register, however,
12 bits of data appear in the order of bit 11 to bit 0; i.e., 12 DCLK cycles should be made before CS returns high.
The data is right-justified.
Interrupt Circuit
Interrupt-control words 1 and 2 are used to program which events cause an interrupt. When any of the events
occur, the associated bit of the event register is set. INTRPT is set whenever an enabled interrupt occurs.
When the event register is read, its contents are first transferred to a buffer and the register is cleared. The bits
are then read out in series. At the end of the read sequence, INTRPT is reset. When an interrupt event occurs
during the read operation, INTRPT remains low for approximately 1 µs and then returns high.
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