TCM8002_08 Datasheet, PDF (11/25 Pages) Texas Instruments – DATA PROCESSOR FOR CELLULAR TELEPHONE

TCM8002
DATA PROCESSOR FOR CELLULAR TELEPHONE
SLWS008C − SEPTEMBER 1994 − REVISED JUNE 1996
PRINCIPLES OF OPERATION
miscellaneous functions
The following paragraphs detail TCM8010 miscellaneous functions shown in the functional block diagram.
TCM8010 Interface
The TCM8010 Interface provides a serial communication channel to the TCM8010 advanced audio processor
using terminals HCS, HCLK, and HDATA.
Write operation:
The TCM8010 address bits and data bits are written in two write operations to the TCM8010
interface with word 1 first and then word 0. On completion of the write to the TCM8010
interface word 0, the data is clocked out to the TCM8010 chip over the 3-wire serial interface.
The TCM8010 interface status bit (status word 2, bit 0) indicates when the interface is active.
Read operation:
The TCM8010 address bits and HCLK speed are written to the TCM8010 interface word 0.
This initiates an A/D conversion and results in retrieval using the 3-bit serial interface. The
status bit (status word 2, bit 0) is set for the duration of the interaction. On completion, the
8-bit result can be read from the TCM8010 result location. The HCLK speed is detailed in
Table 1.
Table 1. TCM8010 HCLK Speed Control Bits (Interface Word 0)
HCLK SPEED
7
6
5
4 ^{CONTROL BITS} 1
0
HCLK SPEED
IN kHz
3
2
0
0
20
TCM8010 Read
0
1
40
0
Address
XX
1
0
80
1
1
160
Counter/Timer
The Counter/Timer is an 8-bit down counter that counts at the bit rate (i.e., 10 kHz for AMPS, 8 kHz for TACS).
This circuit can be configured to repeatedly count down from the programmed coefficient or to count down once
only and stop at zero. A countdown is initiated by a write to the coefficient location. TMZERO can be used to
detect when the counter passes/reaches zero. When the counter/timer is configured to cycle continuously,
TMZERO changes state for one bit period. An interrupt can also be generated.
Watchdog Timer
The watchdog timer provides a timeout of a minimum of 1 second to a maximum of 1.2 seconds. The timer is
initially started by the first write to address 21 (start/restart watchdog). After this first write, timeout is prevented
by writing to the watchdog timer address at intervals not exceeding 1 second.
When timeout occurs, WDOUT pulses low for 100 µs (AMPS operation) or 125 µs (TACS operation) and RFEN
changes state, but the data in the control registers remain unchanged. It is then necessary to reset the TCM8002
to return the RFEN output to its original state.
WDOUT is also held low for the duration of a low input at RESET. WDOUT remains high in its normal (high) state
during a software reset (write to location reset).
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
11