TCM8002_08 Datasheet, PDF (10/25 Pages) Texas Instruments – DATA PROCESSOR FOR CELLULAR TELEPHONE

TCM8002
DATA PROCESSOR FOR CELLULAR TELEPHONE
SLWS008C − SEPTEMBER 1994 − REVISED JUNE 1996
PRINCIPLES OF OPERATION
RX Buffer
The 28-bit output from the BCH Decoder is fed into the RX Buffer, which can then be read by the microprocessor.
Every time new data is available, an interrupt is generated and a status bit is set. The interrupt may be masked.
The data is read in four 8-bit bytes, and when the last byte (least significant bit) is read, the status bit is reset.
Arbitration Logic
During FOCC reception, the arbitration logic uses the busy/idle bits to determine the status of the RECC. The
arbitration logic monitors the busy/idle status of the FOCC at the start of each RECC transmission. A collision
is detected when the status becomes busy within the first 56 bit periods or when it remains idle after 104 bit
periods. When a collision is detected, the arbitration-failure flag in the event register is set and an interrupt can
be generated (depending on interrupt control word 1). RFEN changes state and the transmission of data to
TXOUT is also aborted if bit 5 of control word 1 is set. To reset the state of RFEN and allow the transmission
of data to TXOUT after an arbitration failure, it is necessary to reset the arbitration-fail latch by writing to address
26 (reset arbitration).
SAT Detector/Regenerator
The SAT detection and regeneration circuit takes the square wave at SATIN as its input. The detection and
regeneration functions are performed by a digital phase-locked loop. The regenerated SAT is output at SATOUT.
SAT determination is performed using this circuit and the result is updated every 0.2 seconds and then output
to the microcontroller interface. The SAT color code (SCC) is determined from the frequency measurement and
the result is available from status word 1, bit 6 and bit 7. If the SAT output frequency is outside of the SAT
frequency range, the SAT is considered invalid and zeros are loaded into word 1, bit 6 and bit 7. In low-power
mode (selected by control word 4, bit 0), this functional block can be turned off by control word 1, bit 7.
transmit path
The TCM8002 transmit path includes the following function blocks as given in the functional block diagram:
TX Buffer
The TX Buffer is a 36-bit buffer that is written to by the processor in five write operations. After the fifth write (the
least significant bit), the TX buffer-available status bit is reset. The status bit is set when the transmit data is read
by the TX Encoder.
TX Encoder
The TX Encoder reads the contents of the TX Buffer and then performs BCH encoding, Manchester encoding,
and RECC or RVC frame formatting. The result is output at TXOUT. The encoding and transmit cycle is initiated
by one of the following conditions:
• With the TX Encoder function not active, transmission is initiated by a processor write to the
Commence-TX address.
• With data to be read from the TX Buffer and the TX Encoder active, transmission of the next frame
follows directly after completion of an active frame and the seizure precursor is omitted.
Under processor control, the TX Encoder generates a signaling tone (ST), which is 10 kHz for AMPS and
8 kHz for TACS.
During RVC message transmission or ST transmission, the transmit audio enable output (TAEN) changes state.
The transmit audio circuit in a connected TCM8010 can be automatically controlled via the TCM8010 interface
(see control word 2). During RVC wide-band data transmission, a copy of the previous TCM8010 control word 1
is resent with bit 5 cleared to 0 and bit 6 set to 1. This mutes the transmit audio path and enables the transmit
data path. At the end of data reception, the original TCM8010 control word 1 is resent.
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