TCM8002_08 Datasheet, PDF (17/25 Pages) Texas Instruments – DATA PROCESSOR FOR CELLULAR TELEPHONE

TCM8002
DATA PROCESSOR FOR CELLULAR TELEPHONE
SLWS008C − SEPTEMBER 1994 − REVISED JUNE 1996
PRINCIPLES OF OPERATION
address 0A − PIO3 output word
This sets the state of the PIO3 terminals when configured as outputs.
address 0B − PO4 control word
The eight output terminals HDATA, CLKOUT, HCS, HCLK, RCCBUSY, TMZERO, RAEN, and TAEN can be
independently reconfigured as outputs. Control bits set the terminals as programmable outputs.
address 0C − PO4 output word
This sets the value of the PO4 terminals configured as outputs. RAEN and TAEN remain open-drain outputs
when configured as programmable outputs.
address 20 − commence TX
Writing to address 20 transfers data from the TX Buffer to the TX Encoder and starts the encoding and
transmission of the data.
address 21 − start watchdog
Writing to address 21 starts one cycle of the Watchdog Timer.
address 22 − abort TX
Writing to address 22 immediately stops a transmission sequence that is in progress.
address 23 − clear TX buffer
Writing to address 23 clears the contents of the TX Buffer. This command can be used to stop the automatic
transmission of a second word written to the TX Buffer when the TX Encoder is active. This command does not
stop the complete transmission of the first word.
address 24 − restart frame sync
Writing to address 24 resets the data-recovery circuit, which then uses the acquisition coefficient initially to
achieve bit synchronization to the received data. It can be used when the phone switches to a new FOCC
(forward control channel) to reduce the time taken to acquire bit synchronization. The data-recovery circuit does
not have to wait until it has detected loss of bit synchronization to change from using the lock coefficient to using
the acquisition coefficient.
address 25 − reset
Writing to address 25 performs a device reset. Its function is identical to that of RESET except that it does not
affect WDOUT. The default values listed in the write address map are then loaded.
address 26 − reset arbitration
Writing to address 26 resets the arbitration-failure circuit.
addresses 40 to 44 − TX data words 0 to 4
The data to be transmitted is written to these five addresses, thereby loading the TX Buffer.
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