LM3S618 Datasheet, PDF (9/572 Pages) List of Unclassifed Manufacturers – Microcontroller

Stellaris^® LM3S618 Microcontroller
List of Figures
Figure 1-1. Stellaris LM3S618 Microcontroller High-Level Block Diagram ................................. 35
Figure 1-2. LM3S618 Controller System-Level Block Diagram ................................................. 42
Figure 2-1. CPU Block Diagram ............................................................................................. 45
Figure 2-2. TPIU Block Diagram ............................................................................................ 46
Figure 2-3. Cortex-M3 Register Set ........................................................................................ 48
Figure 2-4. Bit-Band Mapping ................................................................................................ 68
Figure 2-5. Data Storage ....................................................................................................... 69
Figure 2-6. Vector Table ........................................................................................................ 74
Figure 2-7. Exception Stack Frame ........................................................................................ 76
Figure 3-1. SRD Use Example ............................................................................................... 91
Figure 4-1. JTAG Module Block Diagram .............................................................................. 144
Figure 4-2. Test Access Port State Machine ......................................................................... 147
Figure 4-3. IDCODE Register Format ................................................................................... 151
Figure 4-4. BYPASS Register Format ................................................................................... 152
Figure 4-5. Boundary Scan Register Format ......................................................................... 152
Figure 5-1. Basic RST Configuration .................................................................................... 155
Figure 5-2. External Circuitry to Extend Power-On Reset ....................................................... 155
Figure 5-3. Reset Circuit Controlled by Switch ...................................................................... 156
Figure 5-4. Main Clock Tree ................................................................................................ 159
Figure 6-1. Flash Block Diagram .......................................................................................... 212
Figure 7-1. GPIO Module Block Diagram .............................................................................. 231
Figure 7-2. GPIO Port Block Diagram ................................................................................... 234
Figure 7-3. GPIODATA Write Example ................................................................................. 235
Figure 7-4. GPIODATA Read Example ................................................................................. 235
Figure 8-1. GPTM Module Block Diagram ............................................................................ 272
Figure 8-2. 16-Bit Input Edge Count Mode Example .............................................................. 276
Figure 8-3. 16-Bit Input Edge Time Mode Example ............................................................... 277
Figure 8-4. 16-Bit PWM Mode Example ................................................................................ 278
Figure 9-1. WDT Module Block Diagram .............................................................................. 308
Figure 10-1. ADC Module Block Diagram ............................................................................... 332
Figure 10-2.
Figure 10-3.
Figure 10-4.
Figure 10-5.
Differential Sampling Range, V_{IN_ODD} = 1.5 V ...................................................... 336
Differential Sampling Range, V_{IN_ODD} = 0.75 V .................................................... 336
Differential Sampling Range, V_{IN_ODD} = 2.25 V .................................................... 337
Internal Temperature Sensor Characteristic ......................................................... 338
Figure 11-1. UART Module Block Diagram ............................................................................. 369
Figure 11-2. UART Character Frame ..................................................................................... 370
Figure 12-1. SSI Module Block Diagram ................................................................................. 408
Figure 12-2. TI Synchronous Serial Frame Format (Single Transfer) ........................................ 411
Figure 12-3. TI Synchronous Serial Frame Format (Continuous Transfer) ................................ 412
Figure 12-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................... 412
Figure 12-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................. 413
Figure 12-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ......................................... 414
Figure 12-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............... 414
Figure 12-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 415
Figure 12-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 416
Figure 12-10. MICROWIRE Frame Format (Single Frame) ........................................................ 416
July 14, 2014
9
Texas Instruments-Production Data