LM3S618 Datasheet, PDF (516/572 Pages) List of Unclassifed Manufacturers – Microcontroller

Signal Tables
17 Signal Tables
17.1
Important: All multiplexed pins are GPIOs by default, with the exception of the five JTAG pins (PB7
and PC[3:0]) which default to the JTAG functionality.
The following tables list the signals available for each pin. Functionality is enabled by software with
the GPIOAFSEL register. All digital inputs are Schmitt triggered.
■ Signals by Pin Number
■ Signals by Signal Name
■ Signals by Function, Except for GPIO
■ GPIO Pins and Alternate Functions
■ Connections for Unused Signals
Signals by Pin Number
Table 17-1. Signals by Pin Number
Pin Number
1
2
3
4
5
6
Pin Name
ADC0
ADC1
ADC2
ADC3
RST
LDO
Pin Type
I
I
I
I
I
-
7
VDD
-
8
GND
-
9
OSC0
I
10
OSC1
O
PC7
I/O
11
CCP4
I/O
PC6
I/O
12
PhB
I
PC5
I/O
13
CCP1
I/O
PC4
I/O
14
PhA
I
15
VDD
-
16
GND
-
PA0
I/O
17
U0Rx
I
PA1
I/O
18
U0Tx
O
PA2
I/O
19
SSIClk
I/O
Buffer Type^a Description
Analog Analog-to-digital converter input 0.
Analog Analog-to-digital converter input 1.
Analog Analog-to-digital converter input 2.
Analog Analog-to-digital converter input 3.
TTL
System reset input.
Power
Low drop-out regulator output voltage. This pin requires an external
capacitor between the pin and GND of 1 µF or greater.
Power Positive supply for I/O and some logic.
Power Ground reference for logic and I/O pins.
Analog Main oscillator crystal input or an external clock reference input.
Analog
Main oscillator crystal output. Leave unconnected when using a
single-ended clock source.
TTL
GPIO port C bit 7.
TTL
Capture/Compare/PWM 4.
TTL
GPIO port C bit 6.
TTL
QEI phase B.
TTL
GPIO port C bit 5.
TTL
Capture/Compare/PWM 1.
TTL
GPIO port C bit 4.
TTL
QEI phase A.
Power Positive supply for I/O and some logic.
Power Ground reference for logic and I/O pins.
TTL
GPIO port A bit 0.
TTL
UART module 0 receive.
TTL
GPIO port A bit 1.
TTL
UART module 0 transmit.
TTL
GPIO port A bit 2.
TTL
SSI clock.
516
July 14, 2014
Texas Instruments-Production Data