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LM3S618 Datasheet, PDF (28/572 Pages) List of Unclassifed Manufacturers – Microcontroller | |||
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Architectural Overview
â Compact core.
â Thumb-2 instruction set, delivering the high-performance expected of an ARM core in the
memory size usually associated with 8- and 16-bit devices; typically in the range of a few
kilobytes of memory for microcontroller class applications.
â Rapid application execution through Harvard architecture characterized by separate buses
for instruction and data.
â Exceptional interrupt handling, by implementing the register manipulations required for handling
an interrupt in hardware.
â Deterministic, fast interrupt processing: always 12 cycles, or just 6 cycles with tail-chaining
â Memory protection unit (MPU) to provide a privileged mode of operation for complex
applications.
â Migration from the ARM7⢠processor family for better performance and power efficiency.
â Full-featured debug solution
⢠Serial Wire JTAG Debug Port (SWJ-DP)
⢠Flash Patch and Breakpoint (FPB) unit for implementing breakpoints
⢠Data Watchpoint and Trigger (DWT) unit for implementing watchpoints, trigger resources,
and system profiling
⢠Instrumentation Trace Macrocell (ITM) for support of printf style debugging
⢠Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer
â Optimized for single-cycle flash usage
â Three sleep modes with clock gating for low power
â Single-cycle multiply instruction and hardware divide
â Atomic operations
â ARM Thumb2 mixed 16-/32-bit instruction set
â 1.25 DMIPS/MHz
â JTAG
â IEEE 1149.1-1990 compatible Test Access Port (TAP) controller
â Four-bit Instruction Register (IR) chain for storing JTAG instructions
â IEEE standard instructions: BYPASS, IDCODE, SAMPLE/PRELOAD, EXTEST and INTEST
â ARM additional instructions: APACC, DPACC and ABORT
â Integrated ARM Serial Wire Debug (SWD)
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July 14, 2014
Texas Instruments-Production Data
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