LM3S618 Datasheet, PDF (291/572 Pages) List of Unclassifed Manufacturers – Microcontroller

Stellaris^® LM3S618 Microcontroller
Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018
This register allows software to enable/disable GPTM controller-level interrupts. Writing a 1 enables
the interrupt, while writing a 0 disables it.
GPTM Interrupt Mask (GPTMIMR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Offset 0x018
Type R/W, reset 0x0000.0000
31
30
29
28
27
Type RO
RO
RO
RO
RO
Reset
0
0
0
0
0
15
14
13
12
11
reserved
Type RO
RO
RO
RO
RO
Reset
0
0
0
0
0
26
25
24
23
reserved
RO
RO
RO
RO
0
0
0
0
10
9
8
7
CBEIM CBMIM TBTOIM
R/W
R/W
R/W
RO
0
0
0
0
22
21
RO
RO
0
0
6
5
reserved
RO
RO
0
0
20
19
18
17
16
RO
RO
RO
RO
RO
0
0
0
0
0
4
3
2
1
0
RTCIM CAEIM CAMIM TATOIM
RO
R/W
R/W
R/W
R/W
0
0
0
0
0
Bit/Field
31:11
10
Name
reserved
CBEIM
Type
RO
R/W
Reset
0x00
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPTM CaptureB Event Interrupt Mask
The CBEIM values are defined as follows:
Value Description
0 Interrupt is disabled.
1 Interrupt is enabled.
9
CBMIM
R/W
0
GPTM CaptureB Match Interrupt Mask
The CBMIM values are defined as follows:
Value Description
0 Interrupt is disabled.
1 Interrupt is enabled.
8
TBTOIM
R/W
0
GPTM TimerB Time-Out Interrupt Mask
The TBTOIM values are defined as follows:
Value Description
0 Interrupt is disabled.
1 Interrupt is enabled.
7:4
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
July 14, 2014
291
Texas Instruments-Production Data