LM3S618 Datasheet, PDF (17/572 Pages) List of Unclassifed Manufacturers – Microcontroller

Stellaris^® LM3S618 Microcontroller
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ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044 ........................................ 357
ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048 ................................ 360
ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068 ................................ 360
ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088 ................................ 360
ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 ............................... 360
ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C ............................. 361
ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C ............................. 361
ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C ............................ 361
ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC ............................ 361
ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060 ............... 362
ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080 ............... 362
ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064 ........................................ 363
ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084 ........................................ 363
ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 ............... 365
ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 ........................................ 366
ADC Test Mode Loopback (ADCTMLB), offset 0x100 ....................................................... 367
Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 368
Register 1: UART Data (UARTDR), offset 0x000 ............................................................................... 376
Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 378
Register 3: UART Flag (UARTFR), offset 0x018 ................................................................................ 380
Register 4: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 382
Register 5: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 383
Register 6: UART Line Control (UARTLCRH), offset 0x02C ............................................................... 384
Register 7: UART Control (UARTCTL), offset 0x030 ......................................................................... 386
Register 8: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 388
Register 9: UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 390
Register 10: UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 392
Register 11: UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 393
Register 12: UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 394
Register 13: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 396
Register 14: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 397
Register 15: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 398
Register 16: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 399
Register 17: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 400
Register 18: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 401
Register 19: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 402
Register 20: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 403
Register 21: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 404
Register 22: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 405
Register 23: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 406
Register 24: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 407
Synchronous Serial Interface (SSI) ............................................................................................ 408
Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 421
Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 423
Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 425
Register 4: SSI Status (SSISR), offset 0x00C ................................................................................... 426
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 428
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 429
July 14, 2014
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