DS99R421_14 Datasheet, PDF (9/27 Pages) Texas Instruments – 5-43 MHz FPD-Link LVDS (3 Data + 1 Clock) to FPD-Link II LVDS (Embedded Clock DC DCBalanced)

DS99R421
www.ti.com
SNLS264D – JUNE 2007 – REVISED APRIL 2013
Pin #
Pin Name
I/O/PWR
FPD-LINK LVDS RECEIVER INPUT PINS
28, 30, 32
RxIN[2:0]−
LVDS_I
29, 31, 33
RxIN[2:0]+
LVDS_I
34
RxCLKIN−
LVDS_I
35
RxCLKIN+
LVDS_I
OVER SAMPLED INPUT PINS
3-1
OS[2:0]
LVCMOS_I
CONTROL AND CONFIGURATION PINS
4
PWDNB
LVCMOS_I
15
DEN
LVCMOS_I
10
PRE
LVCMOS_I
18
VODSEL
LVCMOS_I
36, 24, 21, 9 RESRVD
BIST MODE PINS
27
BISTEN
LVCMOS_I/O
LVCMOS_I
LVDS SERIALIZER OUTPUT PINS
14
DOUT+
LVDS_O
13
DOUT−
LVDS_O
POWER / GROUND PINS
5
V_DDP1
6
V_SSP1
7
V_DDP0
8
V_SSP0
11
V_DDDR
12
V_SSDR
17
V_DDSER
16
V_SSSER
V_DD
GND
V_DD
GND
V_DD
GND
V_DD
GND
PIN DESCRIPTIONS
Description
LVDS Receiver inverted Data Inputs (−)
LVDS Receiver true Data Inputs (+)
LVDS Receiver inverted reference Clock Inputs.
Used to strobe data at the RxIN inputs and to drive the receiver PLL
LVDS Receiver true reference Clock Inputs.
Used to strobe data at the RxIN inputs and to drive the receiver PLL
Over Sampled Receiver Data Inputs with Schmitt trigger
Power Down Bar
PWDNB = H; Device is Enabled and ON
PWDNB = L; Device is in power down mode (Sleep), LVDS Driver D_OUT (+/-) Outputs are
in TRI-STATE stand-by mode, PLL is shutdown to minimize power consumption.
Data Enable
DEN = H; LVDS Driver Outputs are Enabled (ON).
DEN = L; LVDS Driver Outputs are Disabled (OFF), Serializer LVDS Driver D_OUT (+/-)
Outputs are in TRI-STATE, PLL still operational and locked to TCLK.
Pre-emphasis Level Select
PRE = NC (No Connect); Pre-emphasis is Disabled (OFF).
Pre-emphasis is active when input is tied to VSS through external resistor R_PRE. Resistor
value determines pre-emphasis level. Recommended value R_PRE ≥ 6 kΩ; I_max = [48 /
R_PRE], R_PREmin = 6 kΩ
See Applications Information section for more details.
VOD Level Select
VODSEL = L; LVDS Driver Output is ±500 mV (R_T = 100Ω)
VODSEL = H; LVDS Driver Output is ±900 mV (R_T = 100Ω)
For normal applications, set this pin LOW. For long cable applications where a larger
VOD is required, set this pin HIGH.
See Applications Information section for more details.
Reserved. This pin MUST be tied LOW.
Control Pin for BIST Mode Enable (ACTIVE H)
BISTEN = L; Default at Low, Normal Mode
BISTEN = H; BIST mode active
Note: Sequence order for proper function of BIST mode:
1) DS99R421 BISTEN = H.
2) DS99R421 PLL must be locked (10 ms).
3) DS90UR124 PLL must be locked.
4) Select BISTM error reporting mode on DS90UR124.
5) DS90UR124 switch BISTEN from L to H.
Serializer LVDS True (+) Output.
This output is intended to be loaded with a 100Ω load to the D_OUT+ pin. The interconnect
should be AC Coupled to this pin with a 100 nF capacitor.
Serializer LVDS Inverted (-) Output
This output is intended to be loaded with a 100Ω load to the D_OUT-pin. The interconnect
should be AC Coupled to this pin with a 100 nF capacitor.
Analog Power supply, PLL POWER
Analog Ground, PLL GROUND
Analog Power supply, VCO POWER
Analog Ground, VCO GROUND
Analog Power supply, LVDS OUTPUT POWER
Analog Ground, LVDS OUTPUT GROUND
Digital Power supply, SERIALIZER POWER
Digital Ground, SERIALIZER GROUND
Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: DS99R421
Submit Documentation Feedback
9