DS99R421_14 Datasheet, PDF (17/27 Pages) Texas Instruments – 5-43 MHz FPD-Link LVDS (3 Data + 1 Clock) to FPD-Link II LVDS (Embedded Clock DC DCBalanced)

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OS[2:0]
3
LVDS
DATA0
100:
LVDS
DATA1
100:
LVDS
DATA2
100:
LVDS
CLK
100:
DS99R421
DS99R421
SNLS264D – JUNE 2007 – REVISED APRIL 2013
DOUT+
DOUT-
Previous
Cycle
1 CLK cycle
* Note: bits [0-23] are not physically located in positions shown above since bits [0-23] are scrambled and DC
Balanced
Single Serialized LVDS Bitstream*
Figure 13. LVDS Data Mapping Diagram
DS99R421
DOUT+ 100 nF
100:
DOUT- _{100 nF}
100 nF RIN+
100:
100 nF ^RIN-
Figure 14. AC Coupled Application
Next
Cycle
DS90UR124
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