DS99R421_14 Datasheet, PDF (6/27 Pages) Texas Instruments – 5-43 MHz FPD-Link LVDS (3 Data + 1 Clock) to FPD-Link II LVDS (Embedded Clock DC DCBalanced)

DS99R421
SNLS264D – JUNE 2007 – REVISED APRIL 2013
AC TIMING DIAGRAMS AND TEST CIRCUITS
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RxCLKIN
(Differential)
V_diff = 0V
Previous Cycle
RxIN0
0V
RxIN1
0V
RxIN2
0V
V_diff = 0V
Current Cycle
V_diff = 0V
Figure 3. LVDS Input Checkerboard Pattern
Next
Cycle
DOUT+
10 pF
100:
Differential
80%
Signal
20%
80%
V_diff = 0V
20%
DOUT-
10 pF
V_diff = (DOUT+) - (DOUT-)
t_LLHT
t_LHLT
Figure 4. Serializer LVDS Output Load and Transition Times
RxIN SYMBOL N
SYMBOL N+1
RxCLKIN
SYMBOL N+2
SYMBOL N+3
RCTCD
SYMBOL N+4
D_OUT
SYMBOL N-4
012
23
SYMBOL N-3
012
23
SYMBOL N-2
012
23
SYMBOL N-1
012
23
Figure 5. RxIN to DOUT Delay – RCTCD
SYMBOL N
012
23
6
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