DS99R421_14 Datasheet, PDF(13/27 Page) Texas Instruments – 5-43 MHz FPD-Link LVDS (3 Data + 1 Clock) to FPD-Link II LVDS (Embedded Clock DC DCBalanced)

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DS99R421_14 Datasheet, PDF (13/27 Pages) Texas Instruments – 5-43 MHz FPD-Link LVDS (3 Data + 1 Clock) to FPD-Link II LVDS (Embedded Clock DC DCBalanced)

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DS99R421

www.ti.com

SNLS264D â JUNE 2007 â REVISED APRIL 2013

SERIAL INTERFACE

The serial link between the DS99R421 and the DS90UR124 is intended for a balanced 100 Ohm interconnect.

The link is expected to be terminated at both ends with 100 Ohms and AC coupled.

To establish a source termination and the correct levels, a Driver side termination is required. This is typically

located close to the device pins and is 100 Ohm resistor connected across the driver outputs.

The AC coupling capacitors should be place close to the 100 Ohm termination resistor at both ends of the

interface. For the high-speed LVDS transmission, small footprint packages should be used for the AC coupling

capacitor. This will help minimize degradation of signal quality due to package parasitics. NPO class 1 or X7R

class 2 type capacitors are recommended. 50 WVDC should be the minimum used for best system-level ESD

performance. The most common used capacitor value for the interface is 100 nF (0.1 uF) capacitor.

The DS90UR124 input stage is designed for AC-coupling by providing a built-in AC bias network which sets the

internal VCM to +1.8V. Therefore multiple termination options are possible.

Receiver Termination Option 1

A single 100 Ohm termination resistor is placed across the RINÂ± pins (see Figure 14). This provides the signal

termination at the Receiver inputs. Other options may be used to increase noise tolerance.

Receiver Termination Option 2

For additional EMI tolerance, two 50 Ohm resistors may be used in place of the single 100 Ohm resistor. A small

capacitor is tied from the center point of the 50 Ohm resistors to ground (see Figure 16). This provides a high-

frequency low-impedance path for noise suppression. Value is not critical, 4.7nF maybe used with general

applications.

Receiver Termination Option 3

For high noise environments an additional voltage divider network may be connected to the center point. This

has the advantage of a providing a DC low-impedance path for noise suppression. Use resistor values in the

range of 100â¦-1Kâ¦ for the pullup and pulldown. Ratio the resistor values to bias the center point at 1.8V. For

example (see Figure 17): VDD=3.3V, Rpullup=1Kâ¦, Rpulldown=1.2Kâ¦; or Rpullup=100â¦, Rpulldown=120â¦

(strongest). The smaller values will consume more bias current, but will provide enhanced noise suppression.

FPD LINK INTERFACE

The FPD-Link Interface supports a 3 Data + Clock (21 bit) interface. The interconnect should employ a 100 Ohm

differential pair, as termination is provided internal to the DS99R421. Note that color mapping is extremely

important to review. Color placement of the bits on the FPD-Link Interface will determine which outputs they will

be recovered on. The DS99R421 is expected to reside on the same board as the FPD-Link Serializer (e.g.

DS90C365A or GUI with Integrated FPD-Link Serializer). The DS99R421 supports a limited common mode

range of 525mV to (VDD â VID/2). Typically this is wide enough to support short interconnects.

@SPEED-BIST (BUILT IN SELF TEST)

The DS99R421/ DS90UR124 serial link is equipped with a built-in self-test (BIST) capability to support both

system manufacturing and field diagnostics.

BIST mode is intended to check the entire high-speed serial link at full link-speed, without the use of specialized

and expensive test equipment. This feature provides a simple method for a system host to perform diagnostic

testing of both DS99R421 and DS90UR124. The BIST function is easily configured through the 2 control pins

(BISTEN and BISTM) on the DS90UR124 and one control pin (BISTEN) of the DS99R421. When the BIST mode

is activated, the DS99R421 has the ability to transfer an internally generated PRBS data pattern. This pattern

traverses across interconnecting links to the DS90UR124. The DS90UR124 includes an on-chip PRBS pattern

verification circuit that checks the data pattern for bit errors and reports any errors on the data output pins on the

DS90UR124.

The @SPEED-BIST feature uses 2 control pins (BISTEN and BISTM) on the DS90UR124 Deserializer. The

BISTEN and BISTM pins together determine the functions of the BIST mode. The BISTEN signal (HIGH)

activates the test feature on the DS90UR124. After the BIST mode is enabled on the DS90UR124, toggle the

BISTEN pin HIGH on the DS99R421 for the DS90UR124 Deserializer to start accepting data. An input clock

signal (RxCLKIN) for the DS99R421 must also be applied during the entire BIST operation. Data on RxIN[2:0]

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