DS99R421_14 Datasheet, PDF (12/27 Pages) Texas Instruments – 5-43 MHz FPD-Link LVDS (3 Data + 1 Clock) to FPD-Link II LVDS (Embedded Clock DC DCBalanced)

DS99R421
SNLS264D – JUNE 2007 – REVISED APRIL 2013
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PRE-EMPHASIS
The DS99R421 features a Pre-Emphasis function used to compensate for extra long or lossy transmission
media. Cable drive is enhanced with a user selectable Pre-Emphasis feature that provides additional output
current during transitions to counteract cable loading effects. The transmission distance will be limited by the loss
characteristics and quality of the media.
To enable the Pre-Emphasis function, the “PRE” pin requires one external resistor (Rpre) to Vss in order to set
the additional current level. Options include:
Normal Output (no pre-emphasis) – Leave the PRE pin open
Enhanced Output (pre-emphasis enabled) – connect a resistor on the PRE pin to Vss. Values of the PRE
Resistor should be between 6K Ohm and 100M Ohm. Values less than 6K Ohm should not be used. The amount
of Pre-Emphasis for a given media will depend on the transmission distance and Fmax of the application. In
general, too much Pre-Emphasis can cause over or undershoot at the receiver input pins. This can result in
excessive noise, crosstalk, reduced Fmax, and increased power dissipation. For shorter cables or distances, Pre-
Emphasis is typically not be required. Signal quality measurements should be made at the end of the application
cable to confirm the proper amount of Pre-Emphasis for the specific application.
The Pre-Emphasis circuit increases the drive current to I = 48 / (Rpre). For example if Rpre = 15K Ohm, then the
Pre-Emphasis current is increased by an additional 3.2 mA.
The duration of the current is controlled to precisely one bit by another circuit. If more than one bit value is
repeated in the next cycle(s), the next bit(s) is “de-emphasized”; Pre-Emphasis is turned off (back to the normal
output current level, hence output level is also reduced). This is done to reduce power, and to reduce ISI (Inter-
Symbol Interference).
VOD SELECT
The Serializer Line Driver Differential Output Voltage (VOD) magnitude is selectable. Two levels are provided
and are determined by the state of the VODSEL pin. When this pin is LOW, normal output levels are obtained.
For most application set the VODSEL pin LOW. When this pin is HIGH, the output current is increased to
increase the VOD level. Use this setting only for extra long cable or high-loss interconnects.
OVER-SAMPLED BITS – OS[2:0]
Up to three additional signals maybe sent across the serial link per PCLK. The over-sampled bits are restricted to
be low speed signals and should be less than 1/5 of the frequency of the PCLK. The DS99R421 OS[2:0]
LVCMOS Inputs have wide hysteresis to help prevent glitches. Signals should convey level information only, as
pulse width distortion will occur by the over sampling technique and location of the sampling clock. The three
over sampled bits are mapped to DS90UR124 bits as: OS0 = bit 21, OS1 = bit 22, and OS2 = bit 23. If the OS
bits are not required, internal pull-down will bias the input to a LOW.
COLOR MAPPING
Color mapping is application specific. It is very important to properly match the Pixel bit to the correct data
channel on the DS90UR124 to properly recover the color and control information. See Figure 13. In this example,
the G0 color bit is placed in the RxIN0 channel and is the first bit. The Serializer in the DS99R421 will place this
bit as bit number 6. Thus G0 will be recovered by the DS90UR124 on bit 6. The three over sampled bits are
mapped to DS90UR124 bits as: OS0 = bit 21, OS1 = bit 22, and OS2 = bit 23.
POWERDOWN (SLEEP) MODE
The Powerdown state is a low power sleep mode that the DS99R421 and DS90UR124 may use to reduce power
when no data is being transferred. The PWDNB on the DS99R421 and RPWDNB on the DS90UR124 are used
to set each device into power down mode, which reduces supply current to the µA range. The DS99R421 enters
powerdown when the PWDNB pin is driven LOW. In powerdown, the PLL stops and the outputs go into TRI-
STATE, disabling load current and reducing current supply. To powerup, the DS99R421, PWDNB must be driven
HIGH. When the DS99R421 exits powerdown, its PLL must lock to RxCLKIN before it is ready for the
initialization state. The system must then allow time for initialization before data transfer can begin.
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