DS90C3202_14 Datasheet, PDF (9/27 Pages) Texas Instruments – 3.3V 8 MHz to 135 MHz Dual FPD-Link Receiver

www.ti.com
DS90C3202
SNLS191D – APRIL 2005 – REVISED APRIL 2013
AC Timing Diagrams (continued)
Figure 7. LVCMOS/LVTTL Output Load and Transition Times
2V
PWDNB
V_DD
RCLK IN
3.15V
RPLLS
RCLKOUT
2V
Figure 8. Receiver Phase Lock Loop Wake-up Time
PWDNB
1.5V
Low
RCLK IN
RCLKOUT
RPDD
Low
Figure 9. Powerdown Delay
RCLKIN
Rx IN
RCLKOUT
(RFB=1)
+
VDIFF =
-
0V
+
-
RPDL
1.5V
Rx OUT
Figure 10. Receiver Propagation Delay
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: DS90C3202
Submit Documentation Feedback
9