DS90C3202_14 Datasheet, PDF (12/27 Pages) Texas Instruments – 3.3V 8 MHz to 135 MHz Dual FPD-Link Receiver

DS90C3202
SNLS191D – APRIL 2005 – REVISED APRIL 2013
AC Timing Diagrams (continued)
RCLK OUT
V_DD/2
RCOP
RFB=0
V_DD/2
RFB=1
Balanced RSRC / RHRC
Register addr 29d/1dh bit[2:1]=00b (default)
RCLK OUT
V_DD/2
RSRC
RHRC
V_DD/2
RSRC Increased by 1UI, RHRC Decreased by 1 UI
Register addr 29d/1dh bit[2:1]=01b
RCLK OUT V_DD/2
RSRC
RHRC
V_DD/2
RSRC Decreased by 1UI, RHRC Increased by 1 UI
Register addr 29d/1dh bit[2:1]=10b
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RCLK OUT
V_DD/2
RSRC
RHRC
RSRC Increased by 2UI, RHRC Decreased by 2 UI
V_DD/2 _{Register addr 29d/1dh bit[2:1]=11b}
RXEB,D[6:0]
RXOA,C,E[6:0] ^VDD^/2
V_DD/2
RXEA,C,E[6:0]
RXOB,D[6:0] ^VDD^/2
V_DD/2
Additional +0.5 UI RSRC on
RXEA,C,E[6:0]; RXOB,D[6:0]
-0.5 UI Less RHRC on
RXEA,C,E[6:0]; RXOB,D[6:0]
Figure 16. Receiver RSRC and RHRC Output Setup/Hold Time Adjustment — PTO Enabled
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