DS90C3202_14 Datasheet, PDF (10/27 Pages) Texas Instruments – 3.3V 8 MHz to 135 MHz Dual FPD-Link Receiver

DS90C3202
SNLS191D – APRIL 2005 – REVISED APRIL 2013
AC Timing Diagrams (continued)
RCLKOUT
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RxOUT
RFB = 0
RFB = 1
Figure 11. RFB: LVTTL Level Programmable Strobe Select
Ideal Bit Start
Sampling
Window
Ideal Bit Stop
RITOL
(Left)
RITOL
(Right)
Ideal Strobe Position
( )tBIT
2
t_BIT
(1UI)
RITOL ≥ Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) + ISI (Inter-symbol interference)
Cable Skew—typically 10 ps–40 ps per foot, media dependent
Please see AN-1217 (SNLA053) for more details.
Cycle-to-cycle jitter is less than 100 ps (worse case estimate).
ISI is dependent on interconnect length; may be zero.
Figure 12. Receiver Input Tolerance and Sampling Window
RCLK OUT V_DD/2
RXOA,B,C,D,E[6:0]
RXEA,B,C,D,E[6:0] ^VDD/2
RCOP
RCOH
RCOL
RSRC
RHRC
RFB=0
V_DD/2
RFB=1
V_DD/2
Register address 29d/1dh bit [2:1] = 00b
Figure 13. Receiver RSRC and RHRC Output Setup/Hold Time — PTO Disabled
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