DS90C3202_14 Datasheet, PDF (2/27 Pages) Texas Instruments – 3.3V 8 MHz to 135 MHz Dual FPD-Link Receiver

DS90C3202
SNLS191D – APRIL 2005 – REVISED APRIL 2013
Block Diagram
RXOA-/+
RXOB-/+
RXOC-/+
RXOD-/+
RXOE-/+
RXEA-/+
RXEB-/+
RXEC-/+
RXED-/+
RXEE-/+
7
RXOA[6:0]
7
RXOB[6:0]
7
RXOC[6:0]
7
RXOD[6:0]
7
RXOE[6:0]
7
RXEA[6:0]
7
RXEB[6:0]
7
RXEC[6:0]
7
RXED[6:0]
7
RXEE[6:0]
RCLKIN-/+
RFB
PWDNB
MODE0
MODE1
S2CLK
S2DAT
PLL
RCLKOUT
Figure 1. Receiver Block Diagram
Typical Application Diagram
Host
(PC, Graphics Board, Video Processor)
Video
Source
DE
Pixel Data
Clock
HSYNC
VSYNC
DS90C3201
FPD-Link
Transmitter
LVDS
5 Pairs
5 Pairs
LVDS Clock
2-Wire Serial
Interface
Display
(LCD Monitor, LCD TV, Digital TV)
DS90C3202
FPD-Link
Receiver
DE
Pixel Data
Clock
HSYNC
VSYNC
Digital
Display
www.ti.com
Figure 2. LCD Panel Application Diagram
Functional Description
The DS90C3201 and DS90C3202 are a dual 10-bit color Transmitter and Receiver FPD-Link chipset designed to
transmit data at clocks speeds from 8 to 135 MHz. DS90C3201 and DS90C3202 are designed to interface
between the digital video processor and the display using a LVDS interface. The DS90C3201 transmitter
serializes 2 channels of video data (10-bit each for RGB for each channel, totaling 60 bits) and control signals
(HSYNC, VSYNC, DE and two user-defined signals) along with clock signal to 10 channels of LVDS signals and
transmits them. The DS90C3202 receiver converts 10 channels of LVDS signals into parallel signals and outputs
2
Submit Documentation Feedback
Product Folder Links: DS90C3202
Copyright © 2005–2013, Texas Instruments Incorporated