DS90C3202_14 Datasheet, PDF (22/27 Pages) Texas Instruments – 3.3V 8 MHz to 135 MHz Dual FPD-Link Receiver

DS90C3202
SNLS191D – APRIL 2005 – REVISED APRIL 2013
Address
R/W
RESET
31d/1fh
R/W
None
Bit #
[7:6]
[5]
[4]
[3]
[2]
[1]
[0]
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Description
11; LVTTL Outputs available as long as "NO CLK" is at
HIGH regardless PLL lock or not
10; LVTTL Outputs available after 1K of CLK cycles
detected & PLL generated strobes are within 0.5UI respect
to REFCLK
01; LVTLL Outputs available after 2K of CLK cycles
detected
00: default ; LVTTL Outputs available after 1K of CLK cycles
detected
0: default; to select the size of wait counter between 1K or
2K, default is 1K
I/O disable control for RXO channel A,
1: disable, 0: enable (default)
I/O disable control for RXO channel B,
1 disable, 0: enable (default)
I/O disable control for RXO channel C,
1: disable, 0: enable (default)
I/O disable control for RXO channel D,
1: disable, 0: enable (default)
I/O disable control for RXO channel E,
1: disable, 0: enable (default)
Default Value
0000_0000
22
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