DS90C3202_14 Datasheet, PDF (11/27 Pages) Texas Instruments – 3.3V 8 MHz to 135 MHz Dual FPD-Link Receiver

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DS90C3202
SNLS191D – APRIL 2005 – REVISED APRIL 2013
AC Timing Diagrams (continued)
RCLK OUT
V_DD/2
RCOP
RCOH
RCOL
RFB=0
V_DD/2
RFB=1
RXEB,D[6:0]
RXOA,C,E[6:0]
V_DD/2
V_DD/2
RXEA,C,E[6:0]
RXOB,D[6:0]
V_DD/2
1/2 UI
1/2 UI
RegisterAddress 29d/1dh bit [2:1] = 00b
Figure 14. Receiver RSRC and RHRC Output Setup/Hold Time — PTO Enabled
RCLK OUT
V_DD/2
RCOP
RCOH
RCOL
RFB=0
V_DD/2
RFB=1
Balanced RSRC / RHRC
Register addr 29d/1dh bit[2:1]=00b (default)
RCLK OUT
V_DD/2
RSRC
RHRC
+1 UI
-1 UI
V_DD/2
RSRC Increased by 1UI, RHRC Decreased by 1UI
Register addr 29d/1dh bit[2:1]=01b
RCLK OUT V_DD/2
RSRC
RHRC
-1 UI
+1 UI
V_DD/2
RSRC Decreased by 1UI, RHRC Increased by 1UI
Register addr 29d/1dh bit[2:1]=10b
RCLK OUT
V_DD/2
RSRC
+2 UI
RHRC
-2 UI
RSRC Increased by 2UI, RHRC Decreased by 2UI
V_DD/2 _{Register addr 29d/1dh bit[2:1]=11b}
RXOA,B,C,D,E[6:0]
RXEA,B,C,D,E[6:0]
V_DD/2
V_DD/2
Figure 15. Receiver RSRC and RHRC Output Setup/Hold Time Adjustment — PTO Disabled
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