BQ24735_17 Datasheet, PDF (9/46 Pages) Texas Instruments – 1- to 4-Cell Li+ Battery SMBus Charge Controller for Supporting Turbo Boost Mode With N-Channel Power MOSFET Selector

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bq24735
SLUSAK9B – SEPTEMBER 2011 – REVISED APRIL 2015
Electrical Characteristics (continued)
4.5 V ≤ V_VCC ≤ 24 V, 0°C ≤ T_J ≤ 125°C, typical values are at T_A = 25°C, with respect to GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP MAX
V_{BTST_REFRESH}
Bootstrap refresh comparator threshold
voltage
V_BTST – V_PH when low-side refresh pulse is requested
3.85
4.3
4.7
PWM LOW-SIDE DRIVER (LODRV)
R_{DS_LO_ON}
Low-side driver turnon resistance
R_{DS_LO_OFF}
Low-side driver turnoff resistance
INTERNAL SOFT START
V_REGN = 6 V, I = 10 mA
V_REGN = 6 V, I = 10 mA
7.5
12
0.9
1.4
I_STEP
Soft start current step
In CCM mode 10-mΩ current-sensing resistor
64
UNIT
V
Ω
Ω
mA
7.6 Timing Requirements
ACOK COMPARATOR
V_{ACOK_RISE_DEG}
ACOK rising deglitch (specified by design)
V_VCC > UVLO, V_ACDET rising above 2.4 V,
First time OR ChargeOption() bit [15] = 0
V_VCC > UVLO, V_ACDET rising above 2.4 V,
(NOT First time) AND ChargeOption() bit [15] = 1
(Default)
INPUT OVERCURRENT COMPARATOR (ACOC)⁽¹⁾
t_{ACOC_DEG}
ACOC deglitch time (specified by design)
Voltage across input sense resistor rising to disable
charge
BATTERY DEPLETION COMPARATOR (BAT_DEPL) [1]
t_{BATDEPL_RDEG}
Battery depletion rising deglitch (specified Delay to turn off ACFET and turn on BATFET during
by design)
LEARN cycle
PWM DRIVER TIMING
t_{LOW_HIGH}
Driver dead time from low side to high side
t_{HIGH_LOW}
Driver dead time from high side to low side
INTERNAL SOFT START
t_STEP
Soft start current step time
SMBus TIMING CHARACTERISTICS
t_R
SCLK/SDATA rise time
t_F
SCLK/SDATA fall time
t_W(H)
SCLK pulse width high
t_W(L)
SCLK Pulse Width Low
t_SU(STA)
Setup time for START condition
t_H(STA)
START condition hold time after which first clock pulse is generated
t_SU(DAT)
Data setup time
t_H(DAT)
Data hold time
t_SU(STOP)
Setup time for STOP condition
t_(BUF)
Bus free time between START and STOP condition
F_S(CL)
Clock Frequency
HOST COMMUNICATION FAILURE
t_timeout
SMBus bus release time-out⁽²⁾
t_BOOT
Deglitch for watchdog reset signal
Watchdog time-out period, ChargeOption() bit [14:13] = 01⁽³⁾
t_WDI
Watchdog time-out period, ChargeOption() bit [14:13] = 10⁽³⁾
Watchdog time-out period, ChargeOption() bit [14:13] = 11⁽³⁾ (Default)
MIN TYP MAX UNIT
100
150
200 ms
0.9
1.3
1.7 s
2.3
4.2
6.6 ms
600
ms
20
ns
20
ns
240
μs
1 μs
300 ns
4
50 μs
4.7
μs
4.7
μs
4
μs
250
ns
300
ns
4
µs
4.7
μs
10
100 kHz
25
35 ms
10
ms
35
44
53 s
70
88
105 s
140
175
210 s
(1) User can adjust threshold through SMBus ChargeOption() REG0x12.
(2) Devices participating in a transfer will time out when any clock low exceeds the 25-ms minimum time-out period. Devices that have
detected a time-out condition must reset the communication no later than the 35-ms maximum time-out period. Both a master and a
slave must adhere to the maximum value specified, as it incorporates the cumulative stretch limit for both a master (10 ms) and a slave
(25 ms).
(3) User can adjust threshold through SMBus ChargeOption() REG0x12.
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