BQ24735_17 Datasheet, PDF (19/46 Pages) Texas Instruments – 1- to 4-Cell Li+ Battery SMBus Charge Controller for Supporting Turbo Boost Mode With N-Channel Power MOSFET Selector

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bq24735
SLUSAK9B – SEPTEMBER 2011 – REVISED APRIL 2015
Device Functional Modes (continued)
9.4.2 Continuous Conduction Mode (CCM)
With sufficient charge current the bq24735’s inductor current never crosses zero, which is defined as continuous
conduction mode. The controller starts a new cycle with ramp coming up from 200 mV. As long as EAO voltage
is above the ramp voltage, the high-side MOSFET (HSFET) stays on. When the ramp voltage exceeds EAO
voltage, HSFET turns off and low-side MOSFET (LSFET) turns on. At the end of the cycle, ramp gets reset and
LSFET turns off, ready for the next cycle. There is always break-before-make logic during transition to prevent
cross-conduction and shoot-through. During the dead time when both MOSFETs are off, the body-diode of the
low-side power MOSFET conducts the inductor current.
During CCM mode, the inductor current is always flowing and creates a fixed two-pole system. Having the
LSFET turnon keeps the power dissipation low, and allows safely charging at high currents.
9.4.3 Discontinuous Conduction Mode (DCM)
During the HSFET off time when LSFET is on, the inductor current decreases. If the current goes to zero, the
converter enters Discontinuous Conduction Mode. Every cycle, when the voltage across SRP and SRN falls
below 5 mV (0.5 A on 10 mΩ), the undercurrent protection comparator (UCP) turns off LSFET to avoid negative
inductor current, which may boost the system via the body diode of HSFET.
During the DCM mode the loop response automatically changes. It changes to a single-pole system and the pole
is proportional to the load current.
Both CCM and DCM are synchronous operation with LSFET turnon every clock cycle. If the average charge
current goes below 125 mA on a 10-mΩ current sensing resistor, or the battery voltage falls below 2.5 V, the
LSFET keeps turnoff. The battery charger operates in nonsynchronous mode and the current flows through the
LSFET body diode. During nonsynchronous operation, the LSFET turns on only for a refreshing pulse to charge
the BTST capacitor. If the average charge current goes above 250 mA on a 10-mΩ current-sensing resistor, the
LSFET exits nonsynchronous mode and enters synchronous mode to reduce LSFET power loss.
9.5 Programming
9.5.1 SMBus Interface
The bq24735 device operates as a slave, receiving control inputs from the embedded controller host through the
SMBus interface. The bq24735 uses a simplified subset of the commands documented in System Management
Bus Specification V1.1, which can be downloaded from www.smbus.org. The bq24735 uses the SMBus Read-
Word and Write-Word protocols (see Figure 12) to communicate with the smart battery. The bq24735 performs
only as a SMBus slave device with address 0b00010010 (0x12H) and does not initiate communication on the
bus. In addition, the bq24735 has two identification registers a 16-bit device ID register (0xFFH) and a 16-bit
manufacturer ID register (0xFEH).
SMBus communication is enabled with the following conditions:
• V_VCC is above UVLO.
• V_ACDET is above 0.6 V.
The data (SDA) and clock (SCL) pins have Schmitt-trigger inputs that can accommodate slow edges. Choose
pullup resistors (10 kΩ) for SDA and SCL to achieve rise times according to the SMBus specifications.
Communication starts when the master signals a START condition, which is a high-to-low transition on SDA,
while SCL is high. When the master has finished communicating, the master issues a STOP condition, which is a
low-to-high transition on SDA, while SCL is high. The bus is then free for another transmission. Figure 13 and
Figure 14 show the timing diagram for signals on the SMBus interface. The address byte, command byte, and
data bytes are transmitted between the START and STOP conditions. The SDA state changes only while SCL is
low, except for the START and STOP conditions. Data is transmitted in 8-bit bytes and is sampled on the rising
edge of SCL. Nine clock cycles are required to transfer each byte in or out of the bq24735, because either the
master or the slave acknowledges the receipt of the correct byte during the ninth clock cycle. The bq24735
supports the charger commands as described in Table 2.
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