BQ24735_17 Datasheet, PDF (35/46 Pages) Texas Instruments – 1- to 4-Cell Li+ Battery SMBus Charge Controller for Supporting Turbo Boost Mode With N-Channel Power MOSFET Selector

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bq24735
SLUSAK9B – SEPTEMBER 2011 – REVISED APRIL 2015
11 Power Supply Recommendations
When adapter is attached, and ACOK goes HIGH, the system is connected to adapter through ACFET/RBFET.
An external resistor voltage divider attenuates the adapter voltage before it goes to ACDET. The adapter detect
threshold should typically be programmed to a value greater than the maximum battery voltage, but lower than
the IC maximum allowed input voltage and system maximum allowed voltage.
When adapter is removed, the system is connected to battery through BATFET. Typically the battery depletion
threshold should be greater than the minimum system voltage so that the battery capacity can be fully used for
maximum battery life.
12 Layout
12.1 Layout Guidelines
The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the
components to minimize high-frequency current path loop (see Figure 25) is important to prevent electrical and
magnetic field radiation and high-frequency resonant problems. The following procedure shows a PCB layout
priority list for proper layout. Layout PCB according to this specific order is essential.
1. Place the input capacitor as close as possible to the supply and ground connections of the switching
MOSFET and use shortest copper trace connection. These parts should be placed on the same layer of PCB
instead of on different layers and using vias to make this connection.
2. The IC should be placed close to the gate terminals of the switching MOSFET and keep the gate drive signal
traces short for a clean MOSFET drive. The IC can be placed on the other side of the PCB of switching
MOSFETs.
3. Place the inductor input terminal as close as possible to the output terminal of the switching MOSFET.
Minimize the copper area of this trace to lower electrical and magnetic field radiation but make the trace wide
enough to carry the charging current. Do not use multiple layers in parallel for this connection. Minimize
parasitic capacitance from this area to any other trace or plane.
4. Place the charging current-sensing resistor right next to the inductor output. Route the sense leads
connected across the sensing resistor back to the IC in same layer, close to each other (minimize loop area)
and do not route the sense leads through a high-current path (see Figure 26 for Kelvin connection for best
current accuracy). Place the decoupling capacitor on these traces next to the IC.
5. Place the output capacitor next to the sensing resistor output and ground
6. Output capacitor ground connections must be tied to the same copper that connects to the input capacitor
ground before connecting to system ground.
7. Use a single ground connection to tie charger power ground to charger analog ground. Use analog ground
copper pour just beneath the IC, but avoid power pins to reduce inductive and capacitive noise coupling.
8. Route analog ground separately from power ground. Connect analog ground and connect power ground
separately. Connect analog ground and power ground together, using power pad as the single ground
connection point, or using a 0-Ω resistor to tie analog ground to power ground (power pad should tie to
analog ground in this case if possible).
9. Place the decoupling capacitors next to the IC pins and make trace connection as short as possible.
10. It is critical that the exposed power pad on the backside of the IC package be soldered to the PCB ground.
Ensure that there are sufficient thermal vias directly under the IC, connecting to the ground plane on the
other layers.
11. The via size and number should be enough for a given current path.
See the EVM design for the recommended component placement with trace and via locations. For the QFN
information, see SCBA017 and SLUA271.
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