BQ24735_17 Datasheet, PDF (27/46 Pages) Texas Instruments – 1- to 4-Cell Li+ Battery SMBus Charge Controller for Supporting Turbo Boost Mode With N-Channel Power MOSFET Selector

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10 Application and Implementation
bq24735
SLUSAK9B – SEPTEMBER 2011 – REVISED APRIL 2015
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The bq24725A/735EVM-710 evaluation module (EVM) is a complete charger module for evaluating the bq24735.
The application curves were taken using the bq24725A/735EVM-710. Refer to the EVM user's guide (SLUU507)
for EVM information.
10.2 Typical Application
Adapter +
Adapter -
Ri _*
2W
Ci _*
2.2µF
Reverse
Input
R12
Protection ^1M
Q1 (ACFET)
FDS6680A
C17
2200pF
C16
0.1µF
Q6
BSS138W
R13
3.01M
Q2 (RBFET)
FDS6680A ^{RAC 10mW}
C1
0.1µF
C3
0.1µF
R10
4.02 kW
R11
4.02 kW
C2
0.1µF
ACN
ACP
VCC
BATDRV
R1
430 kW
R2
66.5 kW
+3.3V
HOST SMBus
Dig I/O
ADC
Dig I/O
R3
10 kW
CMSRC
REGN
ACDRV
ACDET
BTST
R8
100 kW
ILIM
R7
316 kW
HIDRV
U1
bq247 35 ^PHASE
R4
10 kW
R5
10 kW
SDA
LODRV
GND
SCL
ACOK
SRP
IOUT PowerPad
SRN
C4
100 pF
EN
EN
D2
BAT54C
R9
10 Ω
C5
1µF
R6
4.02 kW
C6
1µF
D1
BAT54
C7
0.047µF
U2
IMD2A
Total
Csys _*
220µF
SYSTEM
C15
0.01µF
Q5 (BATFET)
FDS6680A
C8
10uF
Q3
Sis412DN
C9
10uF
RSR
10mW
L1
4.7µH
Q4
Sis412DN
C10 C11
10µF 10µF
Pack +
Pack -
R14 _*
10 Ω
R15 _*
7.5 W
C13
0.1µF
C14
0.1µF
F_s = 750 kHz, I_ADPT = 4.096 A, I_CHRG = 2.944 A, I_LIM = 4 A, V_CHRG = 12.592 V, 90-W adapter and 3S2P battery pack
Use 0 Ω for better current-sensing accuracy, use 10-Ω or 7.5-Ω resistor for reversed battery connection protection.
See Negative Output Voltage Protection.
The total Csys is the lump sum of system capacitance. It is not required by charger IC. Use Ri and Ci for adapter hot
plug-in voltage spike damping. See Input Filter Design.
Figure 16. Typical System Schematic With Two NMOS Selectors
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