ADC32RF80_16 Datasheet, PDF (87/136 Pages) Texas Instruments – Dual-Channel, 3-GSPS Telecom Receiver and Feedback Devices

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ADC32RF80, ADC32RF83
SBAS774A – MAY 2016 – REVISED DECEMBER 2016
8.5.8 Digital Gain Page (610005h, M = 1 for Channel A and 610105h, M = 1 for Channel B)
8.5.8.1 Register 0A6h (address = 0A6h), Digital Gain Page
Figure 166. Register 0A6h
7
6
5
4
3
2
1
0
0
0
0
0
DIGITAL GAIN
W-0h
W-0h
W-0h
W-0h
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 54. Register 0A6h Field Descriptions
Bit Field
7-4 0
3-0 DIGITAL GAIN
Type
W
R/W
Reset
0h
0h
Description
Must write 0
These bits apply a digital gain to the ADC data (before the DDC)
up to 11 dB.
0000 = Default
0001 = 1 dB
1011 = 11 dB
Others = Do not use
8.5.9 Main Digital Page Channel A (680000h, M = 1)
8.5.9.1 Register 000h (address = 000h), Main Digital Page Channel A
Figure 167. Register 000h
7
6
5
4
3
0
0
0
0
0
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
2
0
W-0h
1
0
W-0h
0
DIG CORE RESET GBL
R/W-0h
Table 55. Register 000h Field Descriptions
Bit Field
7-1 0
0
DIG CORE RESET GBL
Type
W
R/W
Reset
0h
0h
Description
Must write 0
Pulse this bit (0 →1 →0) to reset the digital core (applies to both
channel A and B).
All Nyquist zone settings take effect when this bit is pulsed.
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