ADC32RF80_16 Datasheet, PDF (63/136 Pages) Texas Instruments – Dual-Channel, 3-GSPS Telecom Receiver and Feedback Devices

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ADC32RF80, ADC32RF83
SBAS774A – MAY 2016 – REVISED DECEMBER 2016
SPI BIT
R/W bit
M bit
P bit
CH bit
ADDR[11:0]
DATA[7:0]
Table 26. SPI Input Description
Read/write bit
DESCRIPTION
SPI bank access
JESD page selection bit
SPI access for a specific channel of the JESD SPI
bank
SPI address bits
SPI data bits
OPTIONS
0 = SPI write
1 = SPI read back
0 = Analog SPI bank (master)
1 = All digital SPI banks (main digital, interleaving,
decimation filter, JESD digital, and so forth)
0 = Page access
1 = Register access
0 = Channel A
1 = Channel B
—
—
Figure 136 shows the SDOUT timing when data are read back from a register. Data are placed on the SDOUT
bus at the SCLK falling edge so that the data can be latched at the SCLK rising edge by the external receiver.
SCLK
tSDOUT
SDOUT
Figure 136. SDOUT Timing
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