ADC32RF80_16 Datasheet, PDF (67/136 Pages) Texas Instruments – Dual-Channel, 3-GSPS Telecom Receiver and Feedback Devices

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ADC32RF80, ADC32RF83
SBAS774A – MAY 2016 – REVISED DECEMBER 2016
8.4.3.4 Serial Register Readout: Digital Bank
Readback of the register in one of the digital banks (as shown in Figure 141) can be accomplished by:
1. Driving the SEN pin low.
2. Selecting the page in the digital page: follow step 2 in the Serial Register Write: Digital Bank section.
3. Set the R/W, M, and P bits to 1, select channel A or channel B, and write the address to be read back.
– JESD digital page: use the CH bit to select channel B (CH = 0) or channel A (CH = 1).
4. Read back the register content on the SDOUT pin. When a page is selected, multiple read backs from the
same page can be done.
SDIN
1
1
R/W M
1
0
Register Address [11:0]
Register Data [7:0] = XX
P CH A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
SCLK
SEN
RESET
SDOUT
D7 D6 D5 D4 D3 D2 D1 D0
SDOUT [7:0]
Figure 141. SPI Read Timing Diagram for the Digital Bank
8.4.3.5 Serial Register Write: Decimation Filter and Power Detector Pages
The decimation filter and power detector pages are special pages that accept direct addressing. The sampling
clock and SYSREF signal are required to properly configure the decimation settings. Registers located in these
pages can be programmed in one SPI cycle (Figure 142).
1. Drive the SEN pin low.
2. Directly write to the decimation filter or power detector pages. To program registers in these pages, set M = 1
and CH = 1. Additionally, address bit A[10] selects the decimation filter page (A[10] = 0) or the power
detector page (A[10] = 1). Address bit A[11] selects channel A (A[11] = 0) or channel B (A[11] = 1).
– Decimation filter page: write address 50xxh for channel A or 58xxh for channel B.
– Power detector page: write address 54xxh for channel A or 5Cxxh for channel B.
Example: Writing address 5001h with 02h selects the decimation filter page for channel A and programs
decimation factor of divide-by-8 (complex output).
SDIN
01
R/W M
0 1 0/1 0/1 0 0
Register Address [7:0]
Register Data [7:0]
P CH A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
SCLK
SEN
RESET
Figure 142. SPI Write Timing Diagram for the Decimation and Power Detector Pages
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