ADC32RF80_16 Datasheet, PDF (1/136 Pages) Texas Instruments – Dual-Channel, 3-GSPS Telecom Receiver and Feedback Devices

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ADC32RF80, ADC32RF83
SBAS774A – MAY 2016 – REVISED DECEMBER 2016
ADC32RF8x Dual-Channel, 3-GSPS Telecom Receiver and Feedback Devices
1 Features
•1 14-Bit, Dual-Channel, 3-GSPS ADC
• Noise Floor: –155 dBFS/Hz
• RF Input Supports Up to 4.0 GHz
• Aperture Jitter: 90 f_S
• Channel Isolation: 95 dB at f_IN = 1.8 GHz
• Spectral Performance (f_IN = 900 MHz, –2 dBFS):
– SNR: 60.1 dBFS
– SFDR: 66-dBc HD2, HD3
– SFDR: 76-dBc Worst Spur
• Spectral Performance (f_IN = 1.85 GHz, –2 dBFS):
– SNR: 58.9 dBFS
– SFDR: 67-dBc HD2, HD3
– SFDR: 76-dBc Worst Spur
• On-Chip Digital Down-Converters:
– Up to 4 DDCs (Dual-Band Mode)
– Up to 3 Independent NCOs per DDC
• On-Chip Input Clamp for Overvoltage Protection
• Programmable On-Chip Power Detectors with
Alarm Pins for AGC Support
• On-Chip Dither
• On-Chip Input Termination
• Input Full-Scale: 1.35 V_PP
• Support for Multi-Chip Synchronization
• JESD204B Interface:
– Subclass 1-Based Deterministic Latency
– 4 Lanes Per Channel at 12.5 Gbps
• Power Dissipation: 3.2 W/Ch at 3.0 GSPS
• 72-Pin VQFN Package (10 mm × 10 mm)
2 Applications
• Multi-Carrier GSM Cellular Infrastructure Base
Stations
• Telecommunications Receivers
• DPD Observation Receivers
• Backhaul Receivers
• RF Repeaters and Distributed Antenna Systems
3 Description
The ADC32RF8x (ADC32RF80 and ADC32RF83) is
a 14-bit, 3-GSPS, dual-channel telecom receiver and
feedback device family that supports RF sampling
with input frequencies up to 4 GHz and beyond.
Designed for high signal-to-noise ratio (SNR), the
ADC32RF8x family delivers a noise spectral density
of –155 dBFS/Hz as well as dynamic range and
channel isolation over a large input frequency range.
The buffered analog input with on-chip termination
provides uniform input impedance across a wide
frequency range and minimizes sample-and-hold
glitch energy.
Each channel can be connected to a dual-band,
digital down-converter (DDC) with up to three
independent, 16-bit numerically-controlled oscillators
(NCOs) per DDC for phase-coherent frequency
hopping. Additionally, the ADC is equipped with front-
end peak and RMS power detectors and alarm
functions to support external automatic gain control
(AGC) algorithms.
The ADC32RF8x supports the JESD204B serial
interface with subclass 1-based deterministic latency
using data rates up to 12.5 Gbps with up to four lanes
per ADC. The device is offered in a 72-pin VQFN
package (10 mm × 10 mm) and supports the
industrial temperature range (–40°C to +85°C).
Device Information⁽¹⁾
PART NUMBER
PACKAGE
BODY SIZE (NOM)
ADC32RF8x
VQFN (72)
10.00 mm × 10.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Block Diagram
INAP/M
Buffer
50
ADC
ADC
ADC
ADC
GPIO1..4
FAST
DET.
CLKINP/M
Digital Block
N
Interleave
Correction
N
NCO
CTRL
NCO
NCO
PLL
DA[0,1]P/M
DA[2,3]P/M
SYNCBP/M
SYSREFP/M
Buffer
INBP/M
50
FAST 0º/180º
DET. Clock
ADC
ADC
A^AD^DC^C
Digital Block
Interleave
Correction
NCO
NCO
N
N
DB[0,1]P/M
DB[2,3]P/M
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.