TMS320DM6467T_17 Datasheet, PDF (84/352 Pages) Texas Instruments – Digital Media System-on-Chip

TMS320DM6467T
SPRS605C – JULY 2009 – REVISED JUNE 2012
www.ti.com
BIT
31:29
28
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24
23:22
21
20
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18
17
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11
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Table 4-2. VDD3P3V_PWDN Register Bit Descriptions
NAME
RESERVED
USBV
CLKOUT
RSV
SPI
VLYNQ
RESERVED
GMII
MII
MCASP1
MCASP0
PCIHPI1
PCIHPI0
GPIO
WDTIM
TIM23
TIM01
PWM1
PWM0
UR2FC
DESCRIPTION
Reserved. Read returns "0".
USB_DRVVBUS Powerdown Control.
0 = I/O cells powered up.
1 = I/O cells powered down.
This bit controls the USB_DRVVBUS/GP[22] pin.
CLKOUT0 Powerdown Control.
This bit controls the CLKOUT0 pin.
Reserved. Read returns "0".
SPI Powerdown Control.
This bit controls the six SPI interface pins: SPI_CLK, SPI_EN, SPI_CS0, SPI_CS1, SPI_SOMI, and
SPI_SIMO.
VLYNQ Powerdown Control.
This bit controls the ten VLYNQ interface pins: VLYNQ_CLOCK, VLYNQ_SCRUN,
VLYNQ_TXD[3:0], and VLYNQ_RXD[3:0].
Reserved. Read returns "0".
GMII Powerdown Control.
This bit controls the ten pins used by GMII (Gigabit) only: RFTCLK, GMTCLK, MTXD[7:4], and
MRXD[7:4].
MII Powerdown Control.
This bit controls the 17 pins used by (G)MII (10/100/1000) and MDIO interfaces: MTCLK,
MTXD[3:0], MTXEN, MCOL, MCRS, MRCLK, MRXD[3:0], MRXDV, MRXER, MDCLK, and MDIO.
McASP1 Powerdown Control.
This bit controls the three McASP1 pins: ACLKX1, AHCLKX1, and AXR1[0].
McASP0 Powerdown Control.
This bit controls the 12 McASP0 pins: ACLKR0, AHCLKR0, AFSR0, ACLKX0, AHCLKX0, AFSX0,
AXR0[3:0], AMUTE0, and AMUTEIN0.
PCI/HPI/EMIFA/ATA Powerdown Control.
This bit controls the 28 pins used by the ATA or PCI`, HPI, or EMIFA. These pins include:
PCI_RST/DA2/GP[13]/EM_A[22], PCI_IDSEL/HDDIR/EM_R/W,
PCI_REQ/DMARQ/GP[11]/EM_CS5, PCI_GNT/DMACK/GP[12]/EM_CS4,
PCI_CBE1/ATA_CS1/GP[32]/EM_A[19], PCI_CBE0/ATA_CS0/GP[33]/EM_A[18],
DIOW/GP[20]/EM_WAIT4/(RDY4/BSY4), IORDY/GP[21]/EM_WAIT3/(RDY3/BSY3),
DIOR/GP[19]/EM_WAIT5/(RDY5/BSY5), DA1/GP[16]/EM_A[21], DA0/GP[17]/EM_A[20],
INTRQ/GP[18]/RSV , PCI_AD[31:16]/DD[15:0]/HD[31:16]/EM_A[15:0]
Defaults to powered up for NOR boot.
PCI/HPI/EMIFA Powerdown Control.
This bit controls the 28 pins used by PCI, HPI, or EMIFA but not shared with ATA. These pins
include: PCI_CLK/GP[10], PCI_DEVSEL/HCNTL1/EM_BA[1], PCI_FRAME/HINT/EM_BA[0],
PCI_IRDY/HRDY/EM_A[17]/(CLE), PCI_TRDY/HHWIL/EM_A[16]/(ALE),
PCI_STOP/HCNTL0/EM_WE, PCI_SERR/HDS1/EM_OE, PCI_PERR/HCS/EM_DQM1,
PCI_PAR/HAS/EM_DQM0, PCI_INTA/EM_WAIT2/(RDY2/BSY2), PCI_CBE3/HR/W/EM_CS3,
PCI_CBE2/HDS2/EM_CS2, PCI_AD[15:0]/HD[15:0]/EM_D[15:0]
Defaults to powered up for NOR boot.
GPIO Powerdown Control.
This bit controls the eight GP[7:0] pins. Defaults to powered up.
WD Timer Powerdown Control.
This bit controls the WD Timer pin TOUT2.
Timer1 Powerdown Control.
This bit controls the three Timer1 pins TINP1L, TOUT1L, and TOUT1U.
Timer0 Powerdown Control.
This bit controls the four Timer0 pins TINP0L, TINP0U, TOUT0L, and TOUT0U.
PWM1 Powerdown Control.
This bit controls the PWM1/TS1_DOUT pin.
PWM0 Powerdown Control.
This bit controls the PWM0/CRG0_PO/TS1_ENAO pin.
UART2 Flow Control Powerdown Control.
This bit controls the URTS2/UIRTX2/TS0_PSTIN/GP[41] and
UCTS2/USD2/CRG0_VCXI/GP[42]/TS1_PSTO pins.
84
Device Configurations
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