TMS320DM6467T_17 Datasheet, PDF (346/352 Pages) Texas Instruments – Digital Media System-on-Chip

TMS320DM6467T
SPRS605C – JULY 2009 – REVISED JUNE 2012
BIT
31:28
27:12
11-1
0
Table 7-148. JTAG ID Register Selection Bit Descriptions
NAME
VARIANT
PART NUMBER
MANUFACTURER
LSB
DESCRIPTION
Variant (4-Bit) value. DM6467T value: 0001 [Silicon Revision 3.0 and later].
Part Number (16-Bit) value. DM6467T value: 1011 0111 0111 0000.
Manufacturer (11-Bit) value. DM6467T value: 0000 0010 111.
LSB. This bit is read as a "1" for DM6467T.
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7.29.2 JTAG Test-Port Electrical Data/Timing
Table 7-149. Timing Requirements for JTAG Test Port^{(1) (2)} (see Figure 7-96)
NO.
1
t_c(TCK)
Cycle time, TCK
2
t_w(TCKH)
Pulse duration, TCK high
3
t_w(TCKL)
Pulse duration, TCK low
4
t_c(RTCK)
Cycle time, RTCK
5
t_w(RTCKH)
Pulse duration, RTCK high
6
t_w(RTCKL)
Pulse duration, RTCK low
7
t_{su(TDIV-RTCKH)}
Setup time, TDI/TMS/TRST valid before RTCK high
8
t_{h(RTCKH-TDIV)}
Hold time, TDI/TMS/TRST valid after RTCK high
9
t_{su(EMUV-TCKH)}
Setup time, EMU[1:0] valid before TCK high
10 t_h(TCKH-EMUV)
Hold time, EMU[1:0] valid after TCK high
(1) T = TCK cycle time in ns. For example, when TCK frequency is 20 MHz, use T = 50 ns.
(2) R = RTCLK cycle time in ns. For example, when RTCK frequency is 20 MHz, use T = 50 ns.
-1G
MIN MAX
20
0.4T
0.4T
20
0.4R
0.4R
12
0
1.5
4
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table 7-150. Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port⁽¹⁾
(see Figure 7-96)
NO.
PARAMETER
11 t_{d(RTCKL-TDOV)}
Delay time, RTCK low to TDO valid
12 t_d(TCKH-EMUV)
Delay time, TCK high to EMU[1:0] valid
(1) T = TCK cycle time in ns. For example, when TCK frequency is 20 MHz, use T = 50 ns.
-1G
MIN MAX
-1
8
2.5 T - 2.5
UNIT
ns
ns
346 Peripheral Information and Electrical Specifications
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