TMS320DM6467T_17 Datasheet, PDF (227/352 Pages) Texas Instruments – Digital Media System-on-Chip

TMS320DM6467T
www.ti.com
SPRS605C – JULY 2009 – REVISED JUNE 2012
7.12 Transport Stream Interface (TSIF)
The DM6467T device includes two independent Transport Stream Interfaces (TSIF0 and TSIF1) with
corresponding Clock Reference Generator (CRGEN) Modules for System Time-Clock Recovery. The TSIF
peripheral supports the following features:
• 1-bit Serial and 8-bit Parallel independent receive and transmit interfaces with both synchronous and
asynchronous modes. (TSIF1 supports Serial mode only.)
• Stream input/output (I/O) speed rate configurable by the I/O clock speed
• ATS (absolute time stamp) detection, correction, and addition modes
• Automatically detects PAT and PMT and reflects assignment to the internal Packet Identification (PID)
table (supported for partial Transfer Stream [TS] mode only; stream type and PID should be one-to-
one mapping)
• PID filter with 7 PID filter tables and stream type assignments
• BYPASS mode implemented so that not only TS data, but any other data can be received or
transmitted by the TSIF module
• Ring buffer control for both writes (8 channels) and reads (1 channel) to/from memory
• Supports “Specific Packet”, indicating boundary of plural program on TS
• Supports Full-TS in only one mode–Semi-Automatic-A mode, allowing communication to the C64x+
CPU.
• Supports Partial-TS in these modes–Semi-Automatic-B mode and Full-Automatic mode (provided
stream type and PID are one-to-one mapping)
For more detailed information on the CRGEN peripheral, see the TMS320DM646x DMSoC Clock
Reference Generator User's Guide (literature number SPRUEQ1).
7.12.1 TSIF Bus Master
The TSIF peripherals each include a bus master interface that accesses the DM646x system bus to
transfer stream receive and transmit data. Table 7-49 shows the memory map for the TSIF master
interfaces.
START ADDRESS
0x0000 0000
0x1000 0000
0x1001 0000
0x1001 4000
0x1001 8000
0x1002 0000
0x1100 0000
0x4200 0000
0x4400 0000
0x4600 0000
0x4800 0000
0x4A00 0000
0x4C00 0000
0x5000 0000
0x8000 0000
0xA000 0000
0xC000 0000
Table 7-49. TSIF0/1 Master Memory Map
END ADDRESS
0x0FFF FFFF
0x1000 FFFF
0x1001 3FFF
0x1001 7FFF
0x1001 FFFF
0x10FF FFFF
0x41FF FFFF
0x43FF FFFF
0x45FF FFFF
0x47FF FFFF
0x49FF FFFF
0x4BFF FFFF
0x4FFF FFFF
0x7FFF FFFF
0x9FFF FFFF
0xBFFF FFFF
0xFFFF FFFF
SIZE
(BYTES)
256M
64K
16K
16K
32K
16256K
784M
32M
32M
32M
32M
32M
64M
768M
512M
512M
1G
TSIF0/1 ACCESS
Reserved
Reserved
ARM RAM 0 (Data)
ARM RAM 1 (Data)
ARM ROM (Data)
Reserved
EMIFA Data (CS2)
EMIFA Data (CS3)
EMIFA Data (CS4)
EMIFA Data (CS5)
Reserved
VLYNQ (Remote Data)
Reserved
DDR2 Memory Controller
Reserved
Reserved
Copyright © 2009–2012, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications 227
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