TMS320DM6467T_17 Datasheet, PDF (5/352 Pages) Texas Instruments – Digital Media System-on-Chip

TMS320DM6467T
www.ti.com
SPRS605C – JULY 2009 – REVISED JUNE 2012
1.3 Functional Block Diagram
Figure 1-1 shows the functional block diagram of the device.
Input
Clock(s)
JTAG Interface
System Control
PLLs/Clock
Generator
Power/Sleep
Controller
Pin
Multiplexing
ARM Subsystem
ARM926EJ-S CPU
16 KB
I-Cache
8 KB
D-Cache
32 KB RAM
8 KB ROM
DSP Subsystem
C64x™ DSP CPU
128 KB L2 RAM
32 KB
32 KB
L1 Pgm L1 Data
High Definition
Video-Imaging
Coprocessor
(HDVICP0)
High Definition
Video-Imaging
Coprocessor
(HDVICP1)
Switched Central Resource (SCR)
Peripherals
EDMA
Serial Interfaces
McASP
I2C
SPI
UART
System
General-
Purpose
Timer
Watchdog
Timer
PWM
CRGEN
VDCE
Connectivity
TSIF
Video
Port I/F
PCI
USB 2.0
(66 MHz)
PHY
VLYNQ
EMAC
With
MDIO
HPI
Program/Data Storage
DDR2 Async EMIF/
Mem Ctlr
NAND/
ATA
(16b/32b) SmartMedia
Figure 1-1. TMS320DM6467T Functional Block Diagram
Copyright © 2009–2012, Texas Instruments Incorporated
Digital Media System-on-Chip (DMSoC)
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