AM1806_16 Datasheet, PDF (84/245 Pages) Texas Instruments – AM1806 ARM® Microprocessor

AM1806
SPRS658F – FEBRUARY 2010 – REVISED MARCH 2014
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PSC0 BYTE
ADDRESS
-
-
-
Table 6-8. Power and Sleep Controller (PSC) Registers (continued)
PSC1 BYTE
ADDRESS
0x01E2 7A74
0x01E2 7A78
0x01E2 7A7C
ACRONYM
MDCTL29
MDCTL30
MDCTL31
REGISTER DESCRIPTION
Module 29 Control Register
Module 30 Control Register
Module 31 Control Register
6.8.1 Power Domain and Module Topology
The device includes two PSC modules.
Each PSC module controls clock states for several of the on chip modules, controllers and interconnect
components. Table 6-9 and Table 6-10 lists the set of peripherals/modules that are controlled by the PSC,
the power domain they are associated with, the LPSC assignment and the default (power-on reset)
module states. See the device-specific data manual for the peripherals available on a given device. The
module states and terminology are defined in Section 6.8.1.1.
Table 6-9. PSC0 Default Module Configuration
LPSC
Number
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Module Name
EDMA3 Channel Controller 0
EDMA3 Transfer Controller 0
EDMA3 Transfer Controller 1
EMIFA (Br7)
SPI 0
MMC/SD 0
ARM Interrupt Controller
ARM RAM/ROM
—
UART 0
SCR0 (Br 0, Br 1, Br 2, Br 8)
SCR1 (Br 4)
SCR2 (Br 3, Br 5, Br 6)
PRUSS
ARM
—
Power Domain
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
—
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
—
Default Module State
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
Enable
—
SwRstDisable
Enable
Enable
Enable
SwRstDisable
SwRstDisable
—
Auto Sleep/Wake Only
—
—
—
—
—
—
—
Yes
—
—
Yes
Yes
Yes
—
—
—
84
Peripheral Information and Electrical Specifications
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