ADC32RF44 Datasheet, PDF (82/134 Pages) Texas Instruments – Dual-Channel, 14-Bit, 2.6-GSPS, Analog-to-Digital Converter

ADC32RF44
SBAS809 – FEBRUARY 2017
9.5.7 Offset Corr Page Channel B (610000h, M = 1)
9.5.7.1 Register 068h (address = 068h), Offset Corr Page Channel B
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Figure 143. Register 068h
7
6
5
4
FREEZE OFFSET
CORR
0
ALWAYS WRITE 1
0
R/W-0h
W-0h
R/W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
3
0
W-0h
2
DIS
OFFSET
CORR
R/W-0h
1
ALWAYS WRITE 1
R/W-0h
0
0
R/W-0h
Table 54. Register 068h Field Descriptions
Bit
7,5,1
Field
FREEZE OFFSET CORR
6
0
5
ALWAYS WRITE 1
4-3 0
2
DIS OFFSET CORR
1
ALWAYS WRITE 1
0
0
Type
R/W
W
R/W
W
R/W
R/W
W
Reset
0h
0h
0h
0h
0h
0h
0h
Description
Use this bit and bits 5 and 1 to freeze the offset estimation
process of the offset corrector; see the Using DC Coupling in
the ADC32RF44 section.
011 = Apply this setting after powering up the device
111 = Offset corrector is frozen, does not estimate offset
anymore, and applies the last computed value.
Others = Do not use
Must write 0
Always write this bit as 1 for the offset correction block to work
properly.
Must write 0
0 = Offset correction block works and removes f_S/8, f_S/4, 3f_S/8,
and f_S/2 spurs
1 = Offset correction block is disabled
Always write this bit as 1 for the offset correction block to work
properly.
Must write 0
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