ADC32RF44 Datasheet, PDF (50/134 Pages) Texas Instruments – Dual-Channel, 14-Bit, 2.6-GSPS, Analog-to-Digital Converter

ADC32RF44
SBAS809 – FEBRUARY 2017
9.4 Device Functional Modes
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9.4.1 Device Configuration
The ADC32RF44 can be configured using a serial programming interface, as described in the Serial Interface
section. In addition, the device has one dedicated parallel pin (PDN) for controlling the power-down modes.
9.4.2 JESD204B Interface
The ADC32RF44 supports device subclass 1 with a maximum output data rate of 12.5 Gbps for each serial
transmitter.
An external SYSREF signal is used to align all internal clock phases and the local multiframe clock to a specific
sampling clock edge. This alignment allows synchronization of multiple devices in a system and minimizes timing
and alignment uncertainty. The SYNCB input is used to control the JESD204B SerDes blocks, as shown in
Figure 110.
Depending on the ADC sampling rate, the JESD204B output interface can be operated with one, two, or four
lanes per ADC channel. The JESD204B setup and configuration of the frame assembly parameters is controlled
through the SPI interface.
SysRef
SYNCB
INA
JESD
204B
JESD204B
D[3:0]
INB
JESD
204B
JESD204B
D[3:0]
Sample Clock
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Figure 110. JESD Signal Overview
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