ADC32RF44 Datasheet, PDF (58/134 Pages) Texas Instruments – Dual-Channel, 14-Bit, 2.6-GSPS, Analog-to-Digital Converter

ADC32RF44
SBAS809 – FEBRUARY 2017
www.ti.com
9.4.3 Serial Interface
The ADC has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial
interface enable), SCLK (serial interface clock), and SDIN (serial interface data) pins. Serially shifting bits into the
device is enabled when SEN is low. SDIN serial data are latched at every SCLK rising edge when SEN is active
(low), as shown in Figure 113. The interface can function with SCLK frequencies from 20 MHz down to low
speeds (of a few hertz) and also with a non-50% SCLK duty cycle, as shown in Table 26.
The SPI access uses 24 bits consisting of eight register data bits, 12 register address bits, and four special bits
to distinguish between read/write, page and register, and individual channel access, as described in Table 27.
Register Address [11:0]
Register Data [7:0]
SDIN
SCLK
SEN
R/W M P CH A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
tSCLK
tDSU
tDH
tSLOADS
tSLOADH
RESET
f_SCLK
t_SLOADS
t_SLOADH
t_DSU
t_DH
t_SDOUT
Figure 113. SPI Timing Diagram
Table 26. SPI Timing Information
SCLK frequency (equal to 1 / t_SCLK)
SEN to SCLK setup time
SCLK to SEN hold time
SDIN setup time
SDIN hold time
Delay between SCLK falling edge to SDOUT
MIN
TYP
1
50
50
10
10
10
MAX
20
UNIT
MHz
ns
ns
ns
ns
ns
58
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