TMS320TCI6482GTZ Datasheet, PDF (81/260 Pages) Texas Instruments – Communications Infrastructure Digital Signal Processor

TMS320TCI6482
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SPRS246K – APRIL 2005 – REVISED MARCH 2012
Table 4-1. SCR Connection Matrix
TCP2 VCP2 McBSPs UTOPIA2 CONFIGURATION SCR VLYNQ PCI
TC0
Y
Y
N
N
N
N
N
TC1
N
N
Y
Y
Y
Y
Y
TC2
N
N
N
N
N
Y
Y
TC3
N
N
N
N
N
Y
Y
EMAC
N
N
N
N
N
N
N
HPI
N
N
N
N
Y
Y
N
PCI
N
N
N
N
Y
Y
N
SRIO ⁽¹⁾
N
N
N
N
Y
N
N
Megamodule
Y
Y
Y
Y
Y
Y
Y
VLYNQ
N
N
N
N
Y
N
N
(1) Applies to both descriptor and data accesses by the SRIO peripheral.
DDR2 MEMORY
CONTROLLER
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
EMIFA
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
MEGAMODULE
Y
Y
Y
Y
Y
Y
Y
Y
N
Y
4.3 Configuration Switch Fabric
Figure 4-2 shows the connection between the C64x+ Megamodule and the configuration switched central
resource (SCR). The configuration SCR is mainly used by the C64x+ Megamodule to access peripheral
registers. The data SCR also has a connection to the configuration SCR which allows masters to access
most peripheral registers. The only registers not accessible by the data SCR through the configuration
SCR are the device configuration registers and the PLL1 and PLL2 controller registers; these can only be
accessed by the C64x+ Megamodule.
The configuration SCR uses 32-bit configuration buses running at SYSCLK2 frequency. SYSCLK2 is
supplied by the PLL1 controller and is fixed at a frequency equal to the CPU frequency divided by 3.
Copyright © 2005–2012, Texas Instruments Incorporated
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